Channel Multiplexer - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

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5.0 English

The Channel Multiplexer multiplexes AXI Address and Data channels over FPGA I/Os. In addition, the AXI Chip2Chip core internally determines a 2:1 or 4:1 width conversion based on the Chip2Chip PHY Width option selected for the cores. Width conversion is used for reduced I/O utilization between the two devices. For more details on width conversion, see User Tab .

The Channel Multiplexer also multiplexes AXI, AXI4-Lite and interrupt interfaces over the same set of FPGA I/Os. The priority round-robin multiplexing in the Chip2Chip core assigns the highest priority to interrupt signals, second highest priority to the low-bandwidth AXI4-Lite interface, and last priority to the AXI interface. The priority round-robin multiplexing is in effect when more than one of these interfaces are active simultaneously.