The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
05/11/2022 |
5.0 |
Updated Table: Interrupt and Status Signals with axi_c2c_config_error_out signal information. |
|
11/24/2020 |
5.0 |
Added the Simulation Speed Up section in the Design Flow Steps chapter. |
|
04/04/2018 |
5.0 |
Added description for C_SIMULATION. |
|
10/04/2017 |
5.0 |
• Added a new feature for handling pending AXI Transactions in-case of Link Failure. • Removed the Disable De-Skew and Disable Clock Shift option from the GUI. • Updated the core to 5.0, as the IP is modified to calculate the correct lanes/IO count for certain combinations of Data Width, ID Width and Address Width. |
|
04/05/2017 |
4.3 |
Added separate parameters to set the ID widths in the slave configuration. |
|
11/18/2015 |
4.2 |
Added support for UltraScale+ architecture-based devices. |
|
09/30/2015 |
4.2 |
Enabled support for UltraScale ™ Architecture based devices that are using Aurora physical layer interface. |
|
04/01/2015 |
4.2 |
• Enhanced support for 128 data width (in aurora interface mode) and 64 address width. • Added User Parameters Table. |
|
11/19/2014 |
4.2 |
• Updated ”Throughput and Latency” in the Product Specification chapter. • Added more details to “Auto-Negotiation” in the Designing with the Core chapter. |
|
10/01/2014 |
4.2 |
• Added support for Aurora 8B/10B IP core. • Clarified maximum ID width restrictions as it relates to Zynq ® -7000 devices. |
|
04/02/2014 |
4.2 |
• Updated core to v4.2. • Added details about integrating the core with the Xilinx ® Aurora IP core using the Vivado ® IP integrator. Included new ports details in “Migrating and Upgrading” appendix. • Added clocking, reset and interface connectivity details for connecting to the Aurora IP core. |
|
12/18/2013 |
4.1 |
Added support for Aurora interface . |
|
10/02/2013 |
4.1 |
• Updated core to v4.1. • Added Example Design and Test Bench chapters. • Added the Migrating and Updating appendix. • Added support for IP integrator. • Changed all signals and ports to lowercase. |
|
03/30/2013 |
4.0 |
• Updated core to v4.0. • Added support for Vivado ® Design Suite. • Removed support for ISE ® Embedded Development Kit (EDK). |
|
12/18/2012 |
3.0 |
• Updated core to v3.00a and ISE Embedded Development Kit (EDK) to v14.4. • Added support for AXI4-Lite. • Added Debugging . |
|
10/25/2012 |
2.1 |
Corrected typo in This Figure . |
|
10/16/2012 |
2.0 |
Xilinx ® initial release. Updated core to v2.00a and ISE Embedded Development Kit (EDK) to v14.3. |
|
07/25/2012 |
1.0 |
Xilinx ® Beta release. |