AXI4 Interface - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

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5.0 English

The AXI Chip2Chip core provides an AXI4 interface to map to AXI Memory Mapped devices in the device general interconnect. AXI Memory Mapped devices can be AXI Master, AXI interconnect, or AXI Slave functions. The AXI Interface can operate in either Common Clock or in Independent clock modes. For more details on clocking and latencies, see General Design Guidelines .

TIP: The AXI4 interface of the Chip2Chip core provides WUSER signals to maintain compatibility with AXI3 interface specifications. Any AXI3 master that supports write interleaving can use the AXI4 WUSER[3:0] signals to map the WID[3:0] signals in AXI3 write data channel.