AXI4-Lite Interfaces - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

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5.0 English

Read from a register that does not have all 0s as a default to verify that the interface is functional. Output s_axi_arready asserts when the read address is valid, and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:

The interface is enabled, and s_axi_lite_aclk / m_axi_lite_aclk are stable when the core is brought out of reset.

The interface is not being held in reset, and the link status output of the core is asserted.

The other interface inputs and outputs are connected and toggling.

The main core clocks are toggling and the link error or multi-bit error interrupt outputs of the core are not asserted.

If the simulation has been run, verify in simulation that the waveform is correct for accessing the AXI4-Lite interface.