Required Constraints - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

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5.0 English

The physical layer is a set of SelectIO™ interface pins that carry source synchronous clock with the data pins.

These I/O pins need I/O Location and I/O Standard constraints. These constraints are board specific and needs to be specified accordingly in the top-level XDC.