Table: Vivado IDE Parameter to User Parameter Relationship shows the relationship between the fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl Console).
Vivado IDE Parameter/Value (1) |
User Parameter/Value (1) |
Default Value |
---|---|---|
AXI Mode |
C_MASTER_FPGA - 1 - 0 |
1 |
Clocking mode -Independent -Common |
C_COMMON_CLK - 0 - 1 |
0 |
AXI-Lite Mode - None - Master AXI-Lite - Slave AXI-Lite |
C_INTERFACE_TYPE - 0 - 1 - 2 |
0 |
Data Width - 32 - 64 - 128 |
C_INTERFACE_TYPE - 32 - 64 - 128 |
32 |
Address Width Range (32 to 64) |
C_AXI_ADDR_WIDTH Range (32 to 64) |
32 |
ID width Range (0 to 24) |
C_AXI_ID_WIDTH *Applicable for master mode C_M_AXI_ID_WIDTH *Applicable for slave mode Range (0 to 24) |
6 |
WUSER Width Range (0 to 4) |
C_AXI_WUSER_WIDTH *Applicable for master mode C_M_AXI_WUSER_WIDTH *Applicable for slave mode Range (0 to 4) |
4 |
PHY Type - SelectIO ™ SDR - SelectIO ™ DDR - AURORA6466B - AURORA8B10B |
C_INTERFACE_TYPE - 0 - 1 - 2 - 3 |
1 |
PHY Clock Frequency (in Mhz) Range (40 to 400) |
C_SELECTIO_PHY_CLK Range (40 to 400) |
100 |
Enable Differential Clock - false - true |
C_USE_DIFF_CLK - 0 - 1 |
0 |
Enable Differential IO Data - false - true |
C_USE_DIFF_IO - 0 - 1 |
0 |
Enable Link Handler - false - true |
C_EN_AXI_LINK_HNDLR - 0 - 1 |
0 |
For faster example design simulation - false - true |
C_SIMULATION |
0 |
Notes: 1. The Vivado IDE parameter value differs from the user parameter value. Such values are shown in this table as indented below the associated parameter. |