The AXI4-Lite functions in the core are implemented with a shared address and data bus approach. This allows AXI4-Lite Master to accept a new write transaction only on completion of previous write transaction. This means it only accepts new writes on receiving a write response from the AXI4-Lite Slave. Similarly, the AXI4-Lite Master accepts a new read transaction only on completion of previous read transaction. This means it only accepts reads after receiving a read response and data from the AXI4-Lite Slave. For more details on the AXI4 Lite clocking and reset, see General Design Guidelines .