General Design Guidelines - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

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5.0 English

The customizable AXI Chip2Chip core provides multiple clocking and I/O interface options. You can determine the frequency at which the interface needs to be operated. Based on the interface frequency, you can select the I/O type by providing the appropriate constraints in the Xilinx constraints file (XDC). Selecting the SelectIO™ interface DDR option doubles the I/O speed without impacting the latency or performance. Based on the selection in the User Tab , additional internal width conversion stages can be enabled. Each 2:1 stage of width conversion can increase bridging latencies and can also impact performance.

In addition, you can select the common clock and independent clock operations. The common clock mode of operation reduces clock domain crossing latencies, and the independent clock mode provides additional clock conversion functionality. Both AXI Chip2Chip Master and AXI Chip2Chip Slave cores can be independently selected for either Common Clock or Independent clock operation. Operating the AXI Chip2Chip core at frequencies greater than AXI interface frequencies (Independent clock operation) reduces the bridging latencies and can improve overall performance of the AXI Chip2Chip bridging function.