Implementing the Example Design - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

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5.0 English

Depending on the board selected, provide XDC constraints for the system clock pins and SelectIO pins of AXI Chip2Chip core. The status signals (Link Status, Multi-Bit Error,  and Link Error) can be mapped to LEDs to show the status of the AXI Chip2Chip cores.

See the AXI Chip2Chip Reference Design for Real-Time Video Application (XAPP1160) [Ref 1] to set the SelectIO pin constraints for AXI Chip2Chip core on KC705 board.