Device Interface Signals - 5.0 English

Single Ended SelectIO ™ Interface

axi_c2c_selio_tx_clk_out

Output

SelectIO ™ FPGA interface clock from Master device to Slave device.

axi_c2c_selio_tx_data_out[m–1:0]

Output

SelectIO ™ FPGA Interface Data from Master device to Slave device. ‘m’ is the number of Output I/Os required for Master-to-Slave device interfacing. For details, see User Tab .

axi_c2c_selio_rx_clk_in

Input

SelectIO ™ FPGA interface clock from Slave device to Master device.

axi_c2c_selio_rx_data_in[m–1:0]

Input

SelectIO ™ FPGA interface signals from Slave device to Master device. ‘m’ is number of Input I/Os required for Slave to Master device interfacing. For details, see User Tab .

Differential SelectIO ™ Interface

axi_c2c_selio_tx_diff_clk_out_p

axi_c2c_selio_tx_diff_clk_out_n

Output

Select IO ™ differential clock from Master to Slave device. Differential clocking is valid when C_USE_DIFF_CLK is set to 1.

axi_c2c_selio_tx_diff_data_out_p[m–1:0]

axi_c2c_selio_tx_diff_data_out_n[m–1:0]

Output

SelectIO ™ differential Data from Master to Slave device. m is the number of Output I/Os required for Master-to-Slave device interfacing. For details, see Chip2Chip PHY Width in Chapter 4.

Differential data is valid when C_USE_DIFF_IO is set to 1.

axi_c2c_selio_rx_diff_clk_in_p

axi_c2c_selio_rx_diff_clk_in_n

Input

Select IO ™ differential clock from Slave to Master device. Differential clocking is valid when C_USE_DIFF_CLK is set to 1.

axi_c2c_selio_rx_diff_data_in_p[m–1:0]

axi_c2c_selio_rx_diff_data_in_n[m–1:0]

Input

SelectIO ™ differential data signals from Slave to Master device. m is number of Input I/Os required for Slave to Master device interfacing. For details, see User Tab . Differential data is valid when C_USE_DIFF_IO is set to 1.

aurora_do_cc

Output

Clock compensation pattern generator signal used by aurora core. Asserted for every 10 µ s intervals. This port is removed in aurora6466b_v10_0.This can be left open.

aurora_pma_init_in

Input

PMA initialization signal. Input signal that initializes the serial transceiver cells.

aurora_pma_init_out

Output

PMA initialization signal to Aurora IP. This signal is generated from the aurora_pma_init_in signal.

aurora_init_clk ⁽¹⁾

Input

Single-ended init_clk_out signal from the Aurora IP.

aurora_mmcm_not_locked

Input

MMCM locked indication from the Aurora IP. This signal indicates that the user clock from the Aurora IP is not stable.

aurora_reset_pb

Output

Reset signal for the Aurora block. This signal should be connected to the reset_pb signal of the Aurora IP.

Notes:

1. For UltraScale and UltraScale+ devices, this clock should be the same as init clock input for Aurora. For more details, see LogiCORE IP Aurora 8B/10B Product Guide (PG046) [Ref 12] and LogiCORE IP Aurora 64B/66B Product Guide (PG074) [Ref 13] .