SelectIO PHY Interface - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

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5.0 English

The AXI Chip2Chip core provides the SelectIO FPGA interface as an interfacing option between the devices. The SelectIO provides minimum latency between the devices and provides SDR or DDR operations. When the SelectIO interface is used, the I/O type and I/O location must be specified in the Xilinx Design Constraints file (XDC).

an optional AXI4-Stream interface to connect to the Aurora IP core (64B/66B or 8B/10B)AXI Chip2Chip core integration with Aurora IP can also be done through the Vivado IP integrator. The Aurora IP core supports the Xilinx® proprietary Aurora protocol layer and implements Xilinx Multi Gigabit Transceivers (MGTs) for high speed serial communications. To mitigate bit errors associated with a high speed serial interface, the AXI Chip2Chip core for this configuration implements a per-lane Hamming ECC code. The Hamming ECC module implements single-bit error correction and multiple (double) bit error detection (SECDED) functions. To connect the AXI Chip2Chip core with the Aurora IP core, the Aurora IP core should be configured in AXI4-Stream mode without CRC check.

For more details on the clocking, reset and other signal connectivity with the Aurora core, see General Design Guidelines .