Clock Frequencies - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

Document ID
Release Date
5.0 English

The recommended frequency for the AXI interface is up to 200 MHz. For the maximum frequency numbers achieved on the SelectIO PHY interface, see Table: Hardware Testing Configuration with a SelectIO FPGA interface in Verification, Compliance, and Interoperability . The clocking mode for the AXI Chip2Chip core needs to be set based on the AXI Interface Frequency and the required SelectIO interface PHY frequency. The required clocking constraints for the AXI Chip2Chip core are listed below:

s_aclk : The AXI interface of the AXI Chip2Chip Master core operates in the s_aclk clock domain.

axi_c2c_phy_clk : axi_c2c_phy_clk is the SelectIO interface PHY clock and is applicable when the AXI Chip2Chip Master core is configured in Independent Clock mode. For Common Clock mode, this clock constraint is not required because the PHY clock is the same as s_aclk .

m_aclk : The AXI interface of the AXI Chip2Chip Slave core operates in the m_aclk clock domain.

s_axi_lite_aclk : AXI4-Lite Master Mode operates in the s_axi_lite_aclk clock domain.

m_axi_lite_aclk : AXI4-Lite Slave Mode operates in the m_axi_lite_aclk clock domain.

idelay_ref_clk : Both the master and slave AXI Chip2Chip cores utilize the IDELAY_CTRL block for SelectIO PHY calibration. The idelay_ref_clk input is the reference clock to the IDELAY_CTRL block. This clock is 200 MHz or 300 MHz (± 10MHz) based on the selected device.

axi_c2c_selio_rx_clk_in : axi_c2c_selio_rx_clk_in is the source synchronous clock of the SelectIO physical layer. This clock pin must be constrained with the PHY clock frequency. When Common Clocking mode is used, this clock runs at the same frequency as s_aclk .