Resets - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

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5.0 English

The AXI Chip2Chip core allows both Master and Slave cores to have independent reset mapping. The link detect FSM ensures the transactions from the Master device (AXI4 and AXI4-Lite) get initiated only when both Master and Slave AXI Chip2Chip cores are out of reset and ready to accept transactions. Reset can also be propagated from Master device to Slave device. In this case, you need to map the reset from Master device to Slave device.

There is no separate reset for the AXI4-Lite interface. The AXI4-Lite interface is brought out of reset when the link detects FSM is in LINKUP state (when the link status output of the core is asserted). All input clocks to the core, including AXI4-Lite clock, must be stable when the core is brought out of reset (when aresetn core input is deasserted).

It is not recommended to reset either Master or Slave AXI Chip2Chip core during normal operation or when Link Status is asserted. For both SelectIO and Aurora interfaces, resetting the Master AXI Chip2Chip results in a link loss condition. If there is a link loss, both AXI Chip2Chip cores perform LINKUP operations to reestablish the link when the Master AXI Chip2Chip core is brought out of reset. However for the SelectIO interface, this reset sequence requires s_aresetn to be propagated from the Master Device to the Slave Device. When the Slave device is reset during normal operations, the link status is deasserted and a link error interrupt is asserted in the Master AXI Chip2Chip core.

An asserted pma_init input performs both a general interconnect and transceiver reset in the Aurora core, and an asserted reset_pb performs only the general interconnect reset in the Aurora core. The pma_init input is required to be connected to the pma_init_in input of AXI Chip2Chip core. The pma_init_out from the AXI Chip2Chip core is required to be connected to the pma_init input of the Aurora core. To comply with the Aurora core recommendations for hot plug operations, an asserted pma_init (for a minimum of single pulse of init_clk width) causes the AXI Chip2Chip to assert the general interconnect reset to the Aurora core. A 26-bit hot plug counter overflow asserts the pma_init to the Aurora core. The general interconnect reset ( reset_pb ) to the Aurora core also gets asserted when an AXI reset is applied to the AXI Chip2Chip core.

Use the following steps for reset removal sequence for Chip2Chip cores:

1. Remove the master Chip2Chip core out of the reset.

2. Remove the slave Chip2Chip core out of the reset.

This ensures successful link bring-up for both Select IO and Aurora Configuration.

Note: The Chip2Chip core implicitly generates a reset sequence for the Aurora configuration, at power on.