Test Bench for the Example Design

Test Bench for the Example Design - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID

PG020

Release Date

2022-06-08

Version

6.3 English

This section contains information about the provided test bench in the Vivado Design Suite.

Figure 5-2: AXI VDMA Example Design Test Bench
X-Ref Target - Figure 5-2

This Figure shows the test bench for the AXI VDMA example design. The top-level test bench generates a 200 MHz clock and drives an initial reset to the example design. The test completes when both status and done bits are driven High.