S2MM_VDMA_IRQ_MASK (S2MM Error Interrupt Mask

S2MM_VDMA_IRQ_MASK (S2MM Error Interrupt Mask – Offset 3Ch) - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID

PG020

Release Date

2022-06-08

Version

6.3 English

This register can mask an interrupt out originating due to SOF Early, End of Line (EOL) Early, SOF Late or EOL Late errors. This register should be used in following way.

1.First, clear all error bits in the S2MM_VDMASR register (bit 4 to bit 14).

2.Then, set/change the S2MM_VDMA_IRQ_MASK register.

Figure 2-11: S2MM_VDMA_IRQ_MASK Register
X-Ref Target - Figure 2-11

Table 2-13: S2MM_VDMA_IRQ_MASK (S2MM Error Interrupt Mask - Offset 3Ch)
Bits	Field Name	Default Value	Access Type	Description
31–4	Reserved		RO	Always read as zero
3	IRQMaskEOLLateErr	0h	R/W	1 = Masks interrupt due to EOLLateErr. 0 = Does not mask interrupt due to EOLLateErr.
2	IRQMaskSOFLateErr	0h	R/W	1 = Masks interrupt due to SOFLateErr. 0 = Does not mask interrupt due to SOFLateErr.
1	IRQMaskEOLEarlyErr	0h	R/W	1 = Masks interrupt due to EOLEarlyErr. 0 = Does not mask interrupt due to EOLEarlyErr.
0	IRQMaskSOFEarlyErr	0h	R/W	1 = Masks interrupt due to SOFEarlyErr. 0 = Does not mask interrupt due to SOFEarlyErr.