MM2S_VDMASR (MM2S VDMA Status Register – Offset 04h) - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID: PG020
Release Date: 2022-06-08
Version: 6.3 English

This register provides the status for the Memory Map to Stream VDMA Channel.

Figure 2-5: MM2S VDMASR Register
X-Ref Target - Figure 2-5

Table 2-7: MM2S_VDMASR Register Details
Bits	Field Name	Default Value	Access Type	Description
31–24	IRQDelayCntSts	00h	RO	Interrupt Delay Count Status. Indicates current interrupt delay time value.
23-16	IRQFrameCntSts	01h	RO	Interrupt Frame Count Status. Indicates current interrupt frame count value.
15	Reserved	0h	RO	Always read as zero.
14	Err_Irq	0h	R/WC	Interrupt on Error. 0 = No error Interrupt. 1 = Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
13	DlyCnt_Irq	0h	R/WC	Interrupt on Delay. 0 = No Delay Interrupt. 1 = Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
12	FrmCnt_Irq	0h	R/WC	Frame Count Interrupt. 0 = No Frame Count Interrupt. 1 = Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
11–8	Reserved	0h	RO	Write has no effect and read as zero.
7	SOFEarlyErr	0h	R/WC	Start of Frame Early Error 0 = No start-of-frame Error 1 = Start of Frame Early Error detected This error occurs if mm2s_fsync is received before the completion of the frame on the streaming interface.
6	VDMADecErr	0h	RO	VDMA Decode Error. This error occurs if the address request is to an invalid address. •0 = No VDMA Decode Errors. •1 = VDMA Decode Error detected. VDMA channel halts.
5	VDMASlvErr	0h	RO	VDMA Slave Error. •0 = No VDMA Slave Errors. •1 = VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
4	VDMAIntErr	0h	R/WC	VDMA Internal Error. 0 = No VDMA Internal Errors. 1 = VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) the channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared). To restart the channel, a soft or hard reset is required. In case (c), the channel does not stop or halt.
3–2	Reserved	0h	RO	Writing to these bits has no effect, and they are always read as zeros.
1	Reserved	0h	RO	Write has no effect and read as zero.
0	Halted	1h	RO	VDMA Channel Halted. Indicates the run/stop state of the VDMA channel. 0 = VDMA channel running 1 = VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.