Port Descriptions - 6.3 English

Clock, Reset and Interrupt Interface Signals

s_axi_lite_aclk

Clock

I

AXI VDMA AXI4-Lite interface clock

m_axi_mm2s_aclk

Clock

I

AXI VDMA MM2S clock

m_axi_s2mm_aclk

Clock

I

AXI VDMA S2MM clock

m_axis_mm2s_aclk

Clock

I

AXI VDMA MM2S AXIS clock

s_axis_s2mm_aclk

Clock

I

AXI VDMA S2MM AXIS clock

axi_resetn

Reset

I

AXI VDMA Reset. Active-Low reset. When asserted Low, resets entire AXI VDMA core. Must be synchronous to s_axi_lite_aclk and asserted for a minimum of sixteen clock cycles.

mm2s_introut

Interrupt

O

0

Interrupt Out for Memory Map to Stream Channel

s2mm_introut

Interrupt

O

0

Interrupt Out for Stream to Memory Map Channel

AXI4-Lite Interface Signals

s_axi_lite*

S_AXI_LITE

-

-

See Appendix A of the Vivado AXI Reference Guide (UG1037)[Ref 1] for the description of AXI4 Signals.

AXI4 Read Interface Signals

m_axi_mm2s*

M_AXI_MM2S

-

-

See Appendix A of the AXI Reference Guide (UG1037) [Ref 1] for the description of AXI4 Signals.

AXI4 Write Interface Signals

m_axi_s2mm*

M_AXI_S2MM

-

-

See Appendix A of the AXI Reference Guide (UG1037) [Ref 1] for the description of AXI4 Signals.

AXI4-Stream Master Interface Signals

m_axis_mm2s*

M_AXIS_MM2S

-

-

See Appendix A of the AXI Reference Guide (UG1037) [Ref 1] for the description of AXI4 Signals.

AXI4-Stream Slave Interface Signals

s_axis_s2mm*

S_AXIS_S2MM

-

-

See Appendix A of the AXI Reference Guide (UG1037) [Ref 1] for the description of AXI4 signals.

Video Synchronization Interface Signals

mm2s_fsync

Frame Sync

I

MM2S Frame Sync Input. When enabled, VDMA operations begin on each falling edge of fsync. AXI VDMA expects this signal to be asserted for one m_axis_mm2s_aclk cycle.

s2mm_fsync

Frame Sync

I

S2MM Frame Sync Input. When enabled, VDMA operations begin on each falling edge of fsync. AXI VDMA expects this signal to be asserted for one s_axis_s2mm_aclk cycle.

Genlock Interface Signals

mm2s_frame_ptr_in(5:0)

Genlock

I

Read (MM2S) Channel Frame Pointer Input.

See Genlock Synchronization for more details on different Genlock modes.

mm2s_frame_ptr_out(5:0)

Genlock

O

0

Read (MM2S) Channel Frame Pointer Output.

See Genlock Synchronization for more details on different Genlock modes.

s2mm_frame_ptr_in(5:0)

Genlock

I

Write (S2MM) Channel Frame Pointer Input.

See Genlock Synchronization for more details on different Genlock modes.

s2mm_frame_ptr_out(5:0)

Genlock

O

0

Write (S2MM) Channel Frame Pointer Output.

See Genlock Synchronization for more details on different Genlock modes.