MM2S Frame Delay and Stride (MM2S_FRMDLY_STRIDE – Offset 0x58) - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID
PG020
Release Date
2022-06-08
Version
6.3 English
Figure 2-15:      MM2S Frame Delay and Stride Register

X-Ref Target - Figure 2-15

pg020_Desc_frmdly_stride_x12339.jpg
Table 2-17:      MM2S FRMDELAY_STRIDE Register Details

Bits

Field Name

Default Value

Access Type

Description

31–29

Reserved

0h

RO

Writing to these bits has no effect, and they are always read as zeros.

28–24

Frame Delay

1h

R/W

Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.

Note:   Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.

23–16

Reserved

0h

RO

Writing to these bits has no effect, and they are always read as zeros.

15–0

Stride

(Bytes)

0h

R/W

Indicates the number of address bytes between the first pixels of each video line.

Note:   A stride value less than MM2S_HSIZE causes data to be corrupted.