MM2S_REG_INDEX (MM2S Register Index – Offset 14h) - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID
PG020
Release Date
2022-06-08
Version
6.3 English

This register is reserved if Frame Buffers selected in the Vivado® Integrated Design Environment (IDE) is less than 17 or when the address space is more than 32 (Write has no effect, read returns 0).

Figure 2-6:      MM2S Register Index

X-Ref Target - Figure 2-6

pg020_mm2s_register_index_1_x13745.jpg
Table 2-8:      MM2S Register Index (MM2S_REG_INDEX – Offset 0x14)

Bits

Field Name

Default/

Reset State

Access

 

31–1

Reserved

0h

RO

Always read as zero

0

MM2S Reg Index

0h

R/W

When Frame Buffers is greater than 16 = Any write or read access between 0x5C to 0x98 accesses the Start Address 1 to 16.

1 = Any write or read access between 0x5C to 0x98 accesses the Start Address 17 to 32.