Frame Buffers - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID
PG020
Release Date
2022-06-08
Version
6.3 English

This option enables selection of the number of frame buffer storage locations to be processed by AXI VDMA. For an address space greater than 32 bits a maximum of 8 frame buffers are allowed.