Memory Map to Stream Register Details - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID: PG020
Release Date: 2022-06-08
Version: 6.3 English

AXI Video Direct Memory Access v6.3 LogiCORE IP Product Guide
IP Facts
Introduction
Features
Overview
Feature Summary
AXI4 Compliant
AXI4 Data Width
AXI4-Stream Data Width
32 Frame Buffers
Data Realignment Engine
Genlock Synchronization
Asynchronous Channels
Frame Sync Options
Dynamic Clock Frequency Change on AXI4-Stream Interface
Frame Advance or Repeat on Error
Vertical Flip
Applications
Unsupported Features
Licensing and Ordering
Product Specification
Performance
Latency
Throughput
Resource Utilization
Port Descriptions
Timing Diagrams
Example Read (MM2S) Path Timing
Example Write (S2MM) Path Timing
Register Space
Endianess
AXI VDMA Register Address Map
Memory Map to Stream Register Details
Register Access Type Description
MM2S_VDMACR (MM2S VDMA Control Register – Offset 00h)
MM2S_VDMASR (MM2S VDMA Status Register – Offset 04h)
MM2S_REG_INDEX (MM2S Register Index – Offset 14h)
PARK_PTR_REG (Park Pointer Register – Offset 28h)
VDMA_VERSION (AXI VDMA Version Register – Offset 2Ch)
Stream to Memory Map Register Detail
S2MM_VDMACR (S2MM VDMA Control Register – Offset 30h)
S2MM_VDMASR (S2MM VDMA Status Register – Offset 34h)
S2MM_VDMA_IRQ_MASK (S2MM Error Interrupt Mask – Offset 3Ch)
S2MM_REG_INDEX (S2MM Register Index – Offset 44h)
MM2S Vertical Size (MM2S_VSIZE – Offset 0x50)
MM2S Horizontal Size (MM2S_HSIZE – Offset 0x54)
MM2S Frame Delay and Stride (MM2S_FRMDLY_STRIDE – Offset 0x58)
MM2S Start Addresses (Offsets 0x5C to Maximum Offset 0x98)
S2MM Vertical Size (S2MM_VSIZE – Offset 0xA0)
S2MM Horizontal Size (S2MM_HSIZE – Offset 0xA4)
S2MM Frame Delay and Stride (S2MM_FRMDLY_STRIDE – Offset 0xA8)
S2MM Start Addresses (Offsets 0xAC to Maximum Offset 0xE8)
ENABLE VERTICAL FLIP (Enable Vertical Flip Register - Offset ECh)
Genlock Synchronization
Genlock Master
Genlock Slave
Dynamic Genlock Master
Dynamic Genlock Slave
Errors
VDMAIntErr
VDMASlvErr
VDMADecErr
Line and Frame Errors
Designing with the Core
General Design Guidelines
Clocking
Frequency
Dynamic Resolution
Resets
Programming Sequence
Interrupts
Design Flow Steps
Customizing and Generating the Core
Basic Options
Address Width (32-64)
Frame Buffers
Enable Write Channel
Memory Map Data Width
Write Burst Size
Stream Data Width
Line Buffer Depth
Enable Read Channel
Memory Map Data Width
Read Burst Size
Stream Data Width
Line Buffer Depth
Advanced Options
Enable Asynchronous Mode
Enable Vertical Flip
Write Channel Options
Fsync Options
Allow Unaligned Transfers
Read Channel Options
GenLock Mode
Allow Unaligned Transfers
User Parameters
Additional Design Information
FRMPTR_STS (MM2S and S2MM Current Frame Pointer Status – Offset 24h)
S2MM HSIZE Status Register S2MM_HSIZE_STATUS (offset 0xF0h)
S2MM VSIZE Status Register S2MM_VSIZE_STATUS (offset 0xF4h)
Output Generation
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Implementing the Example Design
Test Bench for the Example Design
Simulating the Example Design
Setting up the Simulation
Simulation Results
General Use Cases
Updating
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Changes from v6.3 (04/05/2017) to v6.3 (10/04/2017)
Changes from v6.2 to v6.3
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Technical Support
Vivado Design Suite Debug Feature
Hardware Debug
Frame Pointers Gray Code Outputs
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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