Dynamic Resolution - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID
PG020
Release Date
2022-06-08
Version
6.3 English

This feature allows you to dynamically change both the streaming clock and frame format without going through the reset cycle. For example, you will be able to switch between HD1080 to National Television System Committee/Phase Alternating Line (NTSC/PAL) without going through the reset cycle.

Table: Asynchronous Mode Clock Distribution illustrates signal sets and their corresponding clocks in asynchronous mode.

Table 3-1:      Asynchronous Mode Clock Distribution

Clocks

Ports

s_axi_lite_aclk

All s_axi_lite_* Signals

mm2s_introut

s2mm_introut

axi_resetn

m_axi_mm2s_aclk

All m_axi_mm2s_* Signals

m_axi_s2mm_aclk

All m_axi_s2mm_* Signals

m_axis_mm2s_aclk

All m_axis_mm2s_* Signals

mm2s_fsync

mm2s_frame_ptr_in

mm2s_frame_ptr_out

s_axis_s2mm_aclk

All s_axis_s2mm_* Signals

s2mm_prmtr_update

s2mm_frame_ptr_in

s2mm_frame_ptr_out