•AXI4 Compliant
•Primary AXI4 data width support of 32, 64, 128, 256, 512, and 1,024 bits
•Primary AXI4-Stream data width support of multiples of 8 up to 1,024 bits
•Optional Data Realignment Engine
•Optional Genlock Synchronization
•Independent, asynchronous channel operation
•Dynamic clock frequency change of AXI4-Stream interface clocks
•Optional frame advance or repeat on error
•Supports up to 32 frame buffers
•Supports up to 64-bit address space
•Supports Vertical Flip
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LogiCORE IP Facts Table |
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Core Specifics |
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Supported Device Family(1) |
Versal® ACAP UltraScale+™ UltraScale™ Zynq®-7000, 7 Series |
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Supported User Interfaces |
AXI4, AXI4-Lite, AXI4-Stream |
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Resources |
Performance and Resource Utilization web page |
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Provided with Core |
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Design Files(2) |
VHDL |
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Example Design |
Provided |
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Test Bench |
Provided |
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Constraints File |
Provided |
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Simulation Model |
Not Provided |
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Supported |
Standalone and Linux |
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Tested Design Flows(4) |
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Design Entry |
Vivado® Design Suite |
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Simulation |
For supported simulators, see the |
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Synthesis |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 54448 |
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All Vivado IP Change logs |
Master Vivado® IP Change Logs: 72775 |
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Notes: 1.For a complete list of supported devices, see the Vivado IP catalog. 2.Contains a few Verilog files. Top level is VHDL. 3.Standalone driver details can be found in the Vitis directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm). 4.For the supported versions of the tools, see the |
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