This chapter contains information about the provided example design in the Vivado® Design Suite. One of the most common use cases, the triple frame buffer, is discussed as an example in detail.
For detailed information about available example designs for the VDMA core, see AXI Multi-Ported Memory Controller (XAPP739) [Ref 9], Designing High-Performance Video Systems with the AXI Interconnect (XAPP740) [Ref 10], Designing High-Performance Video Systems in 7 Series FPGAs with the AXI Interconnect (XAPP741) [Ref 3], AXI VDMA Reference Design (XAPP742) [Ref 4], and AXI VDMA Reference Design for the Kintex KC705 Evaluation Board (XAPP1218) [Ref 5].
The top module instantiates all components of the core and the example designs that are needed to implement the design in hardware, as shown in This Figure. This includes the clock generator (MMCM), register configuration, data generator, and data checker modules.
This example design demonstrates transactions on the AXI4-Lite, AXI4, and AXI4-Stream interfaces of the device under test (DUT).
Clock generator: The mixed-mode clock manager (MMCM) is used to generate the clocks for the example design. When the DUT is in synchronous mode, MMCM generates a 50 MHz clock for all the AXI interfaces in the example design. When the DUT is in asynchronous mode, the MMCM generates a 50 MHz clock for the AXI4-Lite interface and a 75 MHz clock for the AXI4 and AXI4-Stream interfaces. The DUT and other modules of the example design are kept under reset until the MMCM is locked.
Register configuration: The AXI Traffic Generator core is used to configure the DUT registers in sequence as mentioned in Programming Sequence. For the Read channel, the run/stop and circular_park bits are enabled in the DMACR register. The HSIZE register is configured as (MMAP_DATA_WIDTH/8)*32 bytes. The VSIZE register is configured as 1.
For the Write channel, the run/stop and circular_park bits are enabled in the DMACR register. The HSIZE register is configured as (STRM_DATA_WIDTH/8)*256 bytes. The VSIZE register is configured as 1.
Read path generator: This uses an AXI block RAM which is filled (with a fixed amount of transfers) after MMCM is locked. The MM2S channel reads this AXI block RAM and transfers data to the AXI4-Stream interface.
Read path checker: This module checks that the data is transferred on the AXI4-Stream interface.
Write path generator: When the Write (S2MM) channel is configured, this module drives the transactions (with a fixed amount of transfers) on the AXI4-Stream interface.
Write path checker: This module checks that the data is transferred on the AXI4-Stream interface. Data received on the AXI4 interface is also written into an AXI block RAM.