Example Write (S2MM) Path Timing - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID
PG020
Release Date
2022-06-08
Version
6.3 English

This Figure illustrates example timing on the S2MM channel for Vertical Size = 5 lines, Horizontal Size = 16, bytes, and Stride = 32 bytes. The figure shows the m_axi_s2mm and s_axis_s2mm interfaces.

Dataflow: After the reception of s2mm_fsync, AXI VDMA drives s2mm_fsync_out and s_axis_s2mm_tready to indicate its readiness to receive a frame on the streaming interface. Incoming streaming data is stored in the line buffer and driven onto the mm side by asserting m_axi_s2mm_awvalid and subsequently driving data on m_axi_s2mm_wdata along with m_axi_s2mm_wvalid.

Figure 2-2:      Example S2MM Interface Timing

X-Ref Target - Figure 2-2

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