|
Bits
|
Field Name
|
Default Value
|
Access Type
|
Description
|
|
31–24
|
IRQDelayCntSts
|
00h
|
RO
|
Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|
23-16
|
IRQFrameCntSts
|
00h
|
RO
|
This field indicates the current value of frame count.
|
|
15
|
EOLLateErr
|
0h
|
R/WC
|
End of Line Late Error.
•0 = No End of Line Late Error
•1 = End of Line Late Error detected. VDMA does not halt
This error occurs if the incoming line size is greater than the programmed hsize value. Write 1 to clear.
|
|
14
|
Err_Irq
|
0h
|
R/WC
|
Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated from the AXI VDMA.
0 = No error Interrupt.
1 = Error interrupt detected.
|
|
13
|
DlyCnt_Irq
|
0h
|
R/WC
|
Interrupt on Delay.
0 = No Delay Interrupt.
1 = Delay Interrupt detected.
If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|
12
|
FrmCnt_Irq
|
0h
|
R/WC
|
Frame Count Interrupt.
• 0 = No Frame Count Interrupt.
• 1 = Frame Count Interrupt detected.
If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|
11
|
SOFLateErr
|
0h
|
R/WC
|
Start of Frame Late Error.
•0 = No start-of-frame Late Error
•1 = Start of Frame Late Error detected. VDMA does not halt
This error occurs if the incoming frame size is greater than the programmed vsize value. Write 1 to Clear in flush on fsync mode.
|
|
10–9
|
Reserved
|
0h
|
RO
|
Write has no effect and read as zero.
|
|
8
|
EOLEarlyErr
|
0h
|
R/WC
|
End of Line Early Error.
•0 = No End of Line Early Error
•1 = End of Line Early Error detected. VDMA does not halt.
This error occurs if the incoming line size is lesser than the programmed hsize value. Write a 1 to clear.
|
|
7
|
SOFEarlyErr
|
0h
|
R/WC
|
Start of Frame Early Error.
•0 = No start-of-frame Early Error
•1 = Start of Frame Early Error detected. VDMA does not halt.
This error occurs if incoming frame size is lesser than programmed vsize value. Write 1 to Clear in flush on fsync mode and Read Only otherwise.
|
|
6
|
VDMADecErr
|
0h
|
RO
|
VDMA Decode Error.
•0 = No VDMA Decode Errors.
•1 = VDMA Decode Error detected. VDMA channel halts.
This error occurs if the address request is to an invalid address.
|
|
5
|
VDMASlvErr
|
0h
|
RO
|
VDMA Slave Error.
•0 = No VDMA Slave Errors.
•1 = VDMA Slave Error detected. VDMA Engine halts.
This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|
4
|
VDMAIntErr
|
0h
|
R/WC
|
VDMA Internal Error.
0 = No VDMA Internal Errors.
1 = VDMA Internal Error detected.
This error occurs during one of the following conditions:
(a) HSIZE or VSIZE register were written zeros or
(b) Internal error received from the helper core axi_datamover or
(c) Received frame size is greater or less than programmed vsize (SOFLateErr or SOFEarlyErr)
In case (a) and/or (b) the channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared). To restart the channel, soft or hard reset is required.
In case (c), the channel does not stop or halt.
|
|
3–2
|
Reserved
|
0h
|
RO
|
Writing to these bits has no effect and they are always read as zeros.
|
|
1
|
Reserved
|
0h
|
RO
|
Write has no effect and read as zero.
|
|
0
|
Halted
|
1h
|
RO
|
VDMA Channel Halted.
Indicates the run/stop state of the VDMA channel.
•0 = VDMA channel running
•1 = VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
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