MM2S_VDMACR (MM2S VDMA Control Register – Offset 00h) - 6.3 English

31–24

IRQDelayCount

00h

R/W

This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the MM2S channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet (m_axis_mm2s_tvalid) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.

Setting this value to zero disables the delay counter interrupt.

23-16

IRQFrameCount

01h

R/WC

This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.

When the count reaches zero, an interrupt out is generated by the MM2S channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.

The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01. When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.

15

Repeat_En

0h

R/W

Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master.

0 – Advance to next frame on frame errors

1 – Repeat previous frame on frame errors

14

Err_IrqEn

0h

R/W

Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out.

0 = Error Interrupt disabled

1 = Error Interrupt enabled

13

DlyCnt_IrqEn

0h

R/W

Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out.

0 = Delay Count Interrupt disabled

1 = Delay Count Interrupt enabled

12

FrmCnt_IrqEn

0h

R/WC

Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero.

0 = Frame Count Interrupt disabled

1 = Frame Count Interrupt enabled   

11–8

RdPntrNum

0h

R/W

Indicates the master in control when MM2S channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise.

0000b = Controlling entity is Entity 1

0001b = Controller entity is Entity 2

0010b = Controller entity is Entity 3

and so on.

7

GenlockSrc

1h

R/W

Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair.

0 = External Genlock

1 = Internal Genlock

6–5

Reserved

0h

R/W

Write has no effect on AXI VDMA.

4

FrameCntEn

0h

R/W

Configures the MM2S channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the MM2S channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.

3

GenlockEn

0h

R/W

Enables Genlock or Dynamic Genlock Synchronization.

•0 = Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by MM2S.

•1 = Genlock or Dynamic Genlock Synchronization enabled. MM2S synchronized to Genlock frame input.

Note:   This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.

See Genlock Synchronization for more details on different Genlock modes.

2

Reset

0h

R/W

Soft reset for AXI VDMA MM2S channel. Setting this bit to a 1 causes the AXI VDMA MM2S channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the MM2S channel. After completion of a soft reset all MM2S registers and bits are in the default state. This bit will be zero at the end of the reset cycle.

0 = Normal operation

1 = Reset in progress

1

Circular_Park

1h

R/W

Indicates frame buffer Circular mode or frame buffer Park mode.

•0 = Park Mode– Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.

•1 = Circular Mode – Engine continuously circles through frame buffers.

0

RS

0h

R/W

Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1).

•0 = Stop – VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations.

•1 = Run – Start VDMA operations. The halted bit in the VDMA Status register deasserts to 0 when the VDMA engine begins operations.

Note:   On Run/Stop clear, in-progress stream transfers might terminate early.