This section includes information on using Xilinx tools to customize and generate the core using the Vivado IP catalog.
To access the AXI VDMA, do the following:
1.Open a project by selecting File > Open Project or create a new project by selecting
File > New Project.
2.Open IP Catalog and choose AXI Infrastructure/Video & Image Processing in the View by Function pane.
3.Double-click AXI Video Direct Memory Access to display the AXI VDMA Vivado Integrated Design Environment (IDE).
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 2] and the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 6].
Note: Figures in this chapter are illustrations of the Vivado IDE. This layout might vary from the current version.
If you are customizing and generating the core in the IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 8] for detailed information. Vivado IDE might auto-compute certain configuration values when validating or generating the design, as noted in this section. You can view the parameter value after successful completion of the validate_bd_design command.
