Implementing the Example Design

Implementing the Example Design - 6.3 English

AXI Video Direct Memory Access v6.3 Product Guide (PG020)

Document ID

PG020

Release Date

2022-06-08

Version

6.3 English

After following the steps described in Customizing and Generating the Core, implement the example design as follows:

1.Right-click the core in the Hierarchy window, and select Open IP Example Design.

2.A new window pops up, asking you to specify a directory for the example design. Select a new directory, or keep the default directory.

A new project is automatically created in the selected directory and it is opened in a new Vivado IDE window.

3.In the Flow Navigator (left-side pane), click Run Implementation and follow the directions.

The following tables describe the example files.

Table: Example Design Files lists the HDL files delivered with the example design.

Table 5-1: Example Design Files
Name	Description
axi_vdma_example_top.xdc	Top-level constraints file for the example design.
<component_name>_exdes.vhd	Top-level HDL file for the example design.
clock_gen.vhd	Clock generation module for example design.
fsync_gen_logic.vhd	Frame sync generation module for example design.
axi4_write_master.vhd	Read path data generator module for example design.
axis_data_read.vhd	Read path data checker module for example design.
axis_write_master.vhd	Write path data generator module for example design.
axi_s2mm_read.vhd	Write path data checker module for example design.

Table: Example Demonstration Test Bench File lists the example demonstration test bench file delivered with the example design.

Table 5-2: Example Demonstration Test Bench File
Name	Description
<component_name>_exdes_tb.vhd	Test bench for the example design

Table: Example Design Constraints File lists the example design constraint file delivered with the example design.

Table 5-3: Example Design Constraints File
Name	Description
<component_name>_exdes.xdc	Top level constraints file for the example design.

The XDC delivered with the example design is configured for the KC705 board. The I/O constraints are commented by default. Uncomment them before implementing the example design on the KC705 board.