The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
06/08/2022 |
6.3 |
•Updated Hardware Debug section. •Updated Table: S2MM_VDMASR Register Details. |
|
10/04/2017 |
6.3 |
•Added Spartan-7 support. (Spartan-7 is considered 7 series.) •Added support for Vertical Flip throughout: °Features in IP Facts page °New Vertical Flip section in Chapter 1, Overview °Address Space Offset in Table 2-5 °ENABLE VERTICAL FLIP section in Chapter 2, Product Specification °Enable Vertical Flip user parameter in Table 4-1 •Updated Figure 4-3 showing new Enable Vertical Flip option. •Added Documentation Navigator and Design Hubs to this appendix. |
|
04/05/2017 |
6.3 |
Changed names of several parameters in Table 4-2. See Appendix A, Migrating and Updating. |
|
11/30/2016 |
6.2 |
•Updated description for 18h to 24h address space offset in Table 2-7. •Modified Err_Irq and DlyCnt_Irq Access Type to R/WC. •Moved Additional Design Information from Appendix C to Chapter 4. Design Flow Steps. |
|
10/05/2016 |
6.2 |
•Added a note about the AXI4-Lite write access register to the beginning of the Register Space section. •Added the Added User Parameters section to Chapter 4. |
|
11/18/2015 |
6.2 |
Added support for UltraScale+ families. |
|
04/01/2015 |
6.2 |
•Added support for 64-bit addressing. |
|
04/02/2014 |
6.2 |
•Enabled frame counter and delay counter function by default. •Added FRMPTR_STS, S2MM HSIZE Status, and S2MM VSIZE Status register tables •Updated Figure 2-23 and added Figure 2-24. |
|
12/18/2013 |
6.1 |
Added UltraScale™ architecture support. |
|
10/02/2013 |
6.1 |
•Revision number advanced to 6.1 to align with core version number. •Added two registers to Table 2-8, Register Address Map. •Updated Figure 2-8, S2MM VDMASR Register. •Added new register, S2MM_VDMA_IRQ_MASK. •Changed all occurrences of frm_ptr to frame_ptr. •Modified Steps 1a and 2a. for Triple Frame Buffer Example section. •Modified Step 9 in Hardware Debug section. •Added Note after Table D-4. •Added example design. •Added Table 6-2 and Table 6-3 and associated text. •Added two figures for IP integrator in Chapter 4 and updated existing figures. •Added Important notes to the Memory Map Data Width, Enable Asynchronous Mode, and Stream Data Width descriptions in Chapter 4. •Added new Chapter 7, General Use Case. •Added Table 5-1 and Table 5-2. •Updated Migrating and Upgrading appendix. |
|
03/20/2013 |
1.6 |
•Updated to core version 6.0 and Vivado Design Suite •Removed all information related to Virtex®-6 and Spartan®-6 FPGAs, ISE Design Suite, CORE Generator™, and UCF. •Added Additional Information Design appendix and removed HBlank and VBlank Period for Standard Frames appendix. |
|
12/18/2012 |
1.5 |
•Updated to core version 5.04a, Vivado Design Suite 2012.4, ISE Design Suite, Embedded Edition v14.4, and ISE Design Suite v14.4. •Replaced Figure 1-1 and Figure 1-2 with a single new figure. •Removed Scatter Gather Mode section and replaced with new paragraph. •Updated devices in Table 2-1, Maximum Frequencies •Updated Table 2-4 and 2-5, resource tables •Removed Figure 3-1, Figure 3-3, Figure 3-13, Figure 3-14, and Figure 3-15 •Removed C_S_AXIS_S2MM_TUSER_BITS parameter •Added C_DYNAMIC_RESOLUTION parameter •Removed Dynamic Line Buffer Threshold section. •Updated GUI screen captures. •Added material about Genlock synchronization. •Updated output hierarchy. •Updated Debugging appendix |
|
10/16/2012 |
1.4 |
Updated to core version 5.03a and 14.3 ISE tools. Updated debugging appendix. |
|
07/25/2012 |
1.3 |
Updated to core version 5.02.a and 14.2 ISE tools. Added Vivado tools and Zynq®-7000 support. Updated Error section. Updated many items in the IP Facts table. Added Additional Design section. |
|
04/24/2012 |
1.2 |
Summary of Major Core Changes Added independent fsync control for both MM2S and S2MM channels Added Dynamic Genlock support |
|
01/18/2012 |
1.1 |
Summary of Major Core Changes Added 32 Frame Stores support Added Internal Genlock support Added Frame Sync on TUSER0 support Added additional stream data width support Summary of Major Documentation Changes Removed List of Acronym from Appendix. For the first occurrence of each acronym, spelled out full text. Added supported software drivers to IP Facts table. Created new section Scatter Gather Mode. Reordered the hierarchy of the Register Space section. Reordered the hierarchy of the Designing with the Core section. Added the new section, Triple Frame Buffer Example. Added new Appendix, HBlank and VBlank Periods for Standard Frames |
|
10/19/2011 |
1.0 |
Initial Xilinx release. |