In synchronous mode, all clocks run at the same frequency and are derived from the same source. There are no multicycle or false paths in this design.
In asynchronous mode, all clocks are treated asynchronously to each other and the core will write out appropriate clock domain crossing constraints.
Table: Core Constraints Files lists the files delivered for the core constraints
Name |
Description |
---|---|
<component_name>.xdc |
Core constraints |
<component_name>_clocks.xdc |
Core constraints |
.
The core also delivers constraints for out-of-context (OOC) mode.
Table: OOC Constraints File lists the OOC constraint file for the core.