Test example 1: Interrupt connection check - 2024.1 English

Vitis Tutorials: Platform Creation (XD101)

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2024.1 English

In this test we will make a incorrect design manually and see whether it can report this error or not.

  1. Please follow the instructions in Versal platform creation tutorial-Step1 to create a custom hardware platform. You can skip the optional steps. Before going through Generate block design step, delete the connection between axi_intc_0.irq and pl_ps_irq0 like the following. Then export the platform according to the steps.

missing image

  1. Go to the ref_files directory.

cd ref_files/pl_validation
make all EXTENSIBLE_XSA=/Vitis-Tutorials/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/ref_files/step1_vivado/build/vivado/custom_hardware_platform_hw.xsa  TARGET=hw #the XSA is exported from last step

Please refer to Versal platform creation tutorial-Step3 to burn the image and connect your board.

Expected log on board is as following:
#Beginning test
#Beginning PS to Memory test
     INFO::PS to memory access check: PASS!
#Beginning PS to Kernel (register) test
     INFO::Try to wite MM2S kernel offset is 10, Value is a
     INFO::kernel register  is accessible
     INFO::Kernel register access check: PASS!
#Beginning PL Kernel to Memory test
     INFO::PL kernels are initialized
     INFO::Comparing the data S2MM write memory with the data MM2S read from memory
     INFO::All the data MM2S read from memory equal to the data S2MM write to memory
     INFO::Kernel to memory access check: PASS!
#Beginning to do interrupt check
     INFO::We are trying to move data in interrupt mode
     INFO::GIC and INC are initialized
     INFO::Interrupt is enabled
     ERROR::Interrupt is not detected in PS side
     ERROR::Please check whether the interrupt is exported in your platform and the interrupt connection in Vivado block design!

This is what we expected log. It report the interrupt connection error as expected. You can try with other extensible hardware platforms.