Customize the System Design for Clock and Reset - 2024.1 English

Vitis Tutorials: Vitis Platform Creation

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2024.1 English

The V++ linker can automatically link the clock signals between kernel and platform. The available clock signals in the platform are exported by PFM.CLK property.

For simple designs, interrupt signals can be sourced by the processor’s pl_clk. The limitation is that the processor has a maximum of four pl_clks and their phase is not aligned.

To provide more interrupt signals, or to provide phase-aligned clocks, use the Clocking Wizard.

To add the Clocking Wizard to the block diagram and enable clock signals for the platform, follow these steps:

  1. Add the clocking wizard block to generate three clocks:

    1. Right-click Diagram view and select Add IP.

    2. Search for and add a Clocking Wizard from the IP Search dialog box.

    3. Double-click the clk_wiz_0 IP block to open the Re-Customize IP dialog box.

    4. Click the Output Clocks tab.

    5. Enable clk_out1 through clk_out3 in the Output Clock column. Set the Requested Output Freq as follows:

      • clk_out1 to 100 MHz.

      • clk_out2 to 200 MHz.

      • clk_out3 to 400 MHz.

    6. At the bottom of the dialog box set the Reset Type to Active Low.


    7. Click OK to close the dialog box.

      Note: So now you have set up the clock system for your design. This clock wizard uses the pl_clk as input clock and generates clocks needed for the whole logic design. In this simple design, use a 100 MHz clock as the axi_lite control bus clock. 200 MHz and 400 MHz clocks are reserved for the DPU AXI interface clock and the DPU core clock during the design linking phase. You can modify the clock quantities and frequency to fit your target design. Before exporting the clock, you must create reset signals for each clock because they are needed in clock export setup.**

  2. Add three Processor System Reset blocks corresponding to the three clocks:

    1. Right-click Diagram view and select Add IP.

    2. Search for and add a Processor System Reset from the IP Search dialog box.

    3. Rename the reset block to proc_sys_reset_1 so that it is easy to understand the relationship between reset modules and clock signals.

    4. Select the proc_sys_reset_1 block, type Ctrl-C and Ctrl-V to replicate two modules. They are named as proc_sys_reset_2 and proc_sys_reset_3, by default.

  3. Connect Clocks and Resets:

    1. Click Run Connection Automation to open a dialog box to connect the proc_sys_reset blocks to the clocking wizard clock outputs.

    2. Enable All Automation on the left side of the Run Connection Automation dialog box.

    3. Select clk_in1 on clk_wiz_0, and set the Clock Source to /zynq_ultra_ps_e_0/pl_clk0.

    4. For each proc_sys_reset instance, select the slowest_sync_clk, and set the Clock Source as follows:

      • proc_sys_reset_1 with /clk_wiz_0/clk_out1

      • proc_sys_reset_2 with /clk_wiz_0/clk_out2

      • proc_sys_reset_3 with /clk_wiz_0/clk_out3

    5. On each proc_sys_reset instance, select ext_reset_in, set Board Part Interface to Custom and set the Select Manual Source to /zynq_ultra_ps_e_0/pl_resetn0.

    6. Make sure all checkboxes are enabled, and click OK to close the dialog and create the connections.

    7. Connect all the dcm_locked signals on each proc_sys_reset instance to the locked signal on clk_wiz_0.


  4. Enable clocks for the platform

    1. Go to the Platform Setup tab.

      If it does not open, use menu Window -> Platform Setup to open it.

    2. Click the Clock tab.

    3. Enable all clocks under clk_wiz_0: clk_out1, clk_out2, clk_out3.

    4. Change their ID to 1, 2, and 3.

    5. Set a default clock, and click Is Default for clk_out2.

      After everything is set up, it should report Info: No problem with Clock interface.

      Platform Setup - Clock

      Note: There should be one and only one default clock in the platform. During the v++ linking stage, the linker uses the default clock to connect the IP blocks if there are no user assignments for link configuration.