Clock and Reset - 2023.2 English

Vitis Tutorials: Vitis Platform Creation (XD101)

Document ID
Release Date
2023.2 English

CIPSClock WizardProcSysResetVitis RegionClock 1Reset 1Clock WizardProcSysResetClock 2Reset 2

Figure 5

Static region and dynamic region can have their own clock and reset signals.

The Clock Wizard in static region is required so that the device tree generator (DTG) can generate correct device tree to describe this clock topology.