In this step, run the design through the implementation run and timing closure. You are free to make all design changes as mentioned in Step 4 and changes in the timing constraint is allowed to meet timing. If you encounter any implementation and timing violation or optimization issues, resolve it in this step and take the design to closure as before. After design closure in Vivado is done, the fixed.xsa can be generated by using the Tcl API: write_hw_platform -fixed ./vivado_impl/flat_fixed.xsa. Take the design to closure as in the Vitis integrated flow. After, the design closure is done in Vivado.
Output: The fixed XSA, flat_fixed.xsa, is in the vivado_impl folder.