Enable AXI Interfaces for the Platform - 2024.1 English

Vitis Tutorials: Vitis Platform Creation (XD101)

Document ID
XD101
Release Date
2024-06-19
Version
2024.1 English
  1. Enable AXI Master interfaces from the processing system (PS).

    • Go to Platform Setup tab.

    • Go to AXI Port tab in Platform Setup.

    • Under zynq_ultra_ps_e_0, enable M_AXI_HPM0_FPD and M_AXI_HPM1_FPD. Keep the Memport and sptag default to M_AXI_GP and empty.

    NOTE:

    • M_AXI_GP means general purpose AXI Master interface.

    • sptag is only applicable to AXI slave interfaces.

    • The v++ linker will instantiate AXI Interconnect automatically to connect between PS AXI Master interfaces and slave interfaces of acceleration kernels. One AXI Master interface will connect up to 16 kernels.

  2. Enable AXI Master interfaces from AXI Interconnect.

    • Under ps8_0_axi_periph, click M01_AXI, press Shift and click M07_AXI to multi-select master interfaces from M01_AXI to M07_AXI.

    • Right click the selection and click on Enable.

    • Keep the Memport and sptag default to M_AXI_GP and empty.

    NOTE:

    • v++ will not cascade another level of AXI Interconnect if the AXI master interface is exported from AXI Interconnect IP.

    • AXI Master interfaces from PS and AXI Interconnect are functionally equivalent to the platform.

    • In general, platform designer should export as many as AXI interfaces to the platform. The application developer should decide which interface to use.

  3. Enable AXI Slave interfaces from PS to allow kernels access DDR memory.

    • Under zynq_ultra_ps_e_0, multi-select all AXI slave interfaces: press Ctrl and click S_AXI_HPC0_FPD, S_AXI_HPC1_FPD, S_AXI_HP0_FPD, S_AXI_HP1_FPD, S_AXI_HP2_FPD, S_AXI_HP3_FPD.

    • Right click the selections and select enable.

    • Change Memport of S_AXI_HPC0_FPD and S_AXI_HPC1_FPD to S_AXI_HP because we will not use any coherent features for these interfaces.

    • Type in simple sptag names for these interfaces so that they can be selected by v++ configuration during linking phase. HPC0, HPC1, HP0, HP1, HP2, HP3.

      Platform Setup - AXI Ports