Export Hardware XSA - 2024.1 English

Vitis Tutorials: Vitis Platform Creation

Document ID
XD101
Release Date
2024-05-30
Version
2024.1 English
  1. Validate the block design

    • Click the Validate Design button in the block design Diagram window

    Note: During validation, Vivado reports a critical warning that /axi_intc_0/intr is not connected. This warning can be safely ignored because v++ linker will link kernel interrupt signals to this floating intr signal.

    CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they do not have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
    Please check your design and connect them as needed: 
    /axi_intc_0/intr
    
  2. Create a top module wrapper for the block design.

    • In Source tab, right click system.bd in Design Sources group

    • Select Create HDL Wrapper….

    • Select Let Vivado manage wrapper and auto-update.

    • Click OK to generate wrapper for block design.

  3. Generate the design.

    • Select Generate Block Design from Flow Navigator.

    • Select Synthesis Options to Global. It will skip IP synthesis during generation.

    • Click Generate.

    • Click Generate Bitstream in Flow Navigator window.

    • Click Yes.

  4. Export the platform.

    • Click menu File -> Export -> Export Platform to launch the Export Hardware Platform wizard. This wizard can also be launched by Export Platform button in Flow Navigator or Platform Setup window.

    • Click Next in the first information page.

    • Select Platform Type: Hardware and Hardware Emulation, click Next. If you skipped the emulation setup previously, select Hardware here.

    • Select Platform State: Pre-synthesis, enable Include Bitstream, click Next

    • Input Platform Properties and click Next. For example,

      • Name: kv260_hardware_platform

      • Vendor: xilinx

      • Board: kv260

      • Version: 0.0

      • Description: This platform provides high PS DDR bandwidth and three clocks: 100MHz, 200MHz and 400MHz.

    • Fill in XSA file name: kv260_hardware_platform and keep the export directory as default.

    • Click Finish. kv260_hardware_platform.xsa will be generated. The export path is reported in the Tcl console.

    NOTE: You enable Include Bitstream to fulfill the requirement of the fpga-manager-util package in PetaLinux.

    Alternatively, the above export can be done in Tcl scripts

    # Setting platform properties
    set_property platform.default_output_type "sd_card" [current_project]
    set_property platform.design_intent.embedded "true" [current_project]
    set_property platform.design_intent.server_managed "false" [current_project]
    set_property platform.design_intent.external_host "false" [current_project]
    set_property platform.design_intent.datacenter "false" [current_project]
    # Write pre-synthesis expandable XSA
    write_hw_platform -include_bit -force -file ./kv260_hardware_platform.xsa