Step 7: Generate the XCLBIN - 2024.1 English

The ‘common image’ package (https://account.amd.com/en/forms/downloads/xef.html?filename=xilinx-versal-common-v2024.1_05230256.tar.gz) contains a prebuilt Linux kernel and root file system that can be used with the AMD Versal™ board for embedded design development using the Vitis software platform.

Before starting this tutorial, run the following steps:

1. Go to the directory where you have unzipped the Versal Common Image package.

2. In a Bash shell, run the /Common Images Dir/xilinx-versal-common-v2024.1/environment-setup-cortexa72-cortexa53-xilinx-linux script. This script sets up the SDKTARGETSYSROOT and CXX variables. If the script is not present, you must run the /Common Images Dir/xilinx-versal-common-v2024.1/sdk.sh.

3. Set up your ROOTFS and IMAGE to point to the rootfs.ext4 and Image files located in the /Common Images Dir/xilinx-versal-common-v2024.1 directory.

4. Set up your PLATFORM_REPO_PATHS environment variable to $XILINX_VITIS/base_platforms.

Compile the A72 Host Application: The host code uses XRT (Xilinx Run Time) as an API to talk to the AI Engine and PL kernels. Note that to compile the host code, it is required to use the c++17 package. Ensure your gcc or g++ compiler has the necessary packages installed.

Run the make command to compile the host application to generate host.exe

make host

The PS code written in host.cpp located in the folder sw. The make command compile host.cpp to generate host.exe.

After generating host.exe, run v++ –package to generate .xclbin.

Use the make command to generate the xcilbin using the v++ package command for HW flow:

make package TARGET=hw

The above make command executes the below command:

v++ -p -t hw -f ./hw/build/my_project/vck190_prj_fixed_hw.xsa \
--package.sd_dir ../versal/aie ./aie/libadf.a \
--package.out_dir package.hw \
--package.rootfs ../sw/versal/xilinx-versal/rootfs.ext4 \
--package.sd_file ../sw/versal/xilinx-versal/Image \
--package.sd_file emconfig.json \
--package.bl31_elf ../boot/bl31.elf \
--package.boot_mode sd \
--package.uboot ../boot/u-boot.elf \
--package.sd_file ../xrt/image/boot.scr \
--package.sd_file host.exe \
--package.dtb ../boot/system.dtb \
-o vck190_vitis_design_hw.xclbin 

To run the design on hardware, refer to the Building and Packaging section in UG1393.

Use the make command to generate the xcilbin using the v++ package command for HW Emulation flow: make package TARGET=hw_emu

The above make command executes the below command:

emconfigutil --platform ./hw/build/my_project/vck190_prj_fixed_hw_emu.xsa --nd 1;\
v++ -p -t hw_emu -f ./hw/build/my_project/vitis_design_fixed_hw_emu.xsa \
--package.sd_dir ../sw/versal/aie ./aie/libadf.a \
--package.out_dir package.hw_emu \
--package.rootfs ../sw/versal/xilinx-versal/rootfs.ext4 \
--package.sd_file ../sw/versal/xilinx-versal/Image \
--package.sd_file emconfig.json \
--package.bl31_elf ../boot/bl31.elf \
--package.boot_mode sd \
--package.uboot ../boot/u-boot.elf \
--package.sd_file ../xrt/image/boot.scr \
--package.sd_file host.exe \
--package.defer_aie_run \
--package.dtb ../boot/system.dtb \
-o vck190_vitis_design_hw_emu.xclbin 

To run the hardware emulation, execute the below steps after .xclbin generation:

make run

You can see in the terminal, that data is received well in stream_in IP. Reading the register to check the number of packets received, it is random as we are checking status through PS randomly. Reading the error register to confirm, any error is occurred during transaction. Message: “TEST IS DONE” concludes the hardware emulation flow.