Vitis Tutorials: Vitis Platform Creation (XD101) - 2024.1 English

Document ID: XD101
Release Date: 2024-06-19
Version: 2024.1 English

Vitis Tutorials: Vitis Platform Creation (XD101)
What is a Platform?
Platform Creation Example Quick Access
Platform Creation Tutorials
Design Tutorials
Feature Tutorials
Feature Tutorials
Incorporating Stream Interfaces
Kernel Modifications
1. Include necessary file headers.
2. Define the AXI stream data type and add the dds process function
3. Add more ports to the kernel functions
4. Add the declaration of the two ports
4. Add a piece of logic to call the dds process function
Host Modifications
1. Include necessary file headers.
2. Create a new cl_mem buffer
3. Bond the buffer with new arguments of the kernel
4. Map the new buffer to a pointer
5. Read data from DDR
6. Save the data into a file
7. Unmap the buffer object
PetaLinux Building and System Customization
Prepare the base platform
Create a PetaLinux Project
Customize Root File System, Kernel, Device Tree and U-boot
Update the Device tree
Add EXT4 rootfs support
Build PetaLinux Images
Fast Track
Hardware Design Fast Iteration with Vitis Export to Vivado
Introduction
We are creating the custom BDC based platform using the tcl script. The Vitis Export to Vivado flow supports BDC-based platform only.
Objectives
Recommended design development flow steps
DESIGN FILES
Design Flow
Step 1 : Create the hardware design in Vivado
Step 2 Create the software components in Vitis
Step 3: Import VMA into Vivado project
Step 4: Changes in the Vivado design after the VMA import
Step 5-1: Use Case 1 : Vivado design changes doesn’t require any PLIO interface change.
Step 5-2: Use Case 2: Vivado design changes that require PLIO interface change
Step 6: Generate the Fixed XSA
Step 7: Generate the XCLBIN
Summary
Support
Hardware Design Validation
Overview
Extensible platform validation general outline
Platform hardware validation
Stage I Base bootable design verification
Step 1: Prepare a hardware design
Step 2: Validate the hardware design
Test1: Go through implementation
Test2: Validate PDI on Hardware
Test3: Peripheral bare-metal test
Stage II Extensible platform interface verification
Step 1: Prepare a Hardware Platform
Step 2: Utilize the V++ linker to link a kernel and generate fixed XSA file
Step 3: Create a platform with standalone domain
Step 4: Create application base on the platform
Extensible platform validation demonstration
Test example 1: Interrupt connection check
Test Example 2: AIE test
Support
Design Tutorials
Create Vitis Platforms for Zynq UltraScale+ MPSoC
Step 1: Create Hardware Platform
Create the Base Vivado Project from Preset
Customize the System Design for Clock and Reset
Add Interrupt Support
Enable AXI Interfaces for the Platform
Emulation Setup (Optional)
Modify the IP address in address editor (Optional)
Export Hardware XSA
Fast Track
Next Steps
Step 2: Create Vitis Software Platform
Prepare the Common Images
Create the Device Tree File
Create a Vitis Platform
Fast Track
Next Steps
Step 3: Test the Platform
Test 1: Read Platform Info
Test 2: Run Vector Addition Application
Fast Track for Vector Addition
Congratulations
Next Steps
Iteration Guidelines
Create a Vitis Platform for Custom Versal Boards
Step 1: Create a Hardware Platform for Customer's VCK190
Create the Vivado Project
Configure the Block
Add the Constraint File
Modify the IP address in address editor (Optional)
Review the Versal Extensible Platform Example Part_base Platform Setup
Review the Simulation Model
Export Hardware XSA
Validate the Output of Step 1
Fast Track
Next Step
Step 2: Create Vitis Software Platform
Prepare the Common Images
Create the Device Tree File
Create the Vitis Platform
Validate the Output of Step 2
Fast Track
Next Step
Step 3: Run Application on the Platform
Application 1: Run a PL Acceleration Application
Application 2: Run an AIE + PL Acceleration Application Project
Next Steps
Iteration Guidelines
Frequently Asked Questions
Why can’t my platform boot on hardware?
Why can’t my platform boot on hardware emulation?
Why can’t my platform support hardware emulation?
PLM IPI Issue
When is the AIE app and PL kernel being programmed?
Why does my AIE system application hang?
Versal DFX Platform Creation Tutorial
Step 1: Create the Hardware Design
Vivado Design Creation
Project Creation
DFX Platform Design Submodule Explanation
Memory Subsystem
Control Subsystem
AI Engine Subsystem
Interrupt Subsystem
Clock and Reset
Modify the IP address in address editor (Optional)
Export Hardware Emulation XSA
Export Hardware XSA
Fast Track
Next Step
References
Step 2: Create the Software Components and the Vitis DFX Platform
Generating Device Tree
Add AI Engine Information to the system-user.dtsi File
Generate the Base Device Tree from the Static XSA
Creating the Vitis Platform
Prepare for Platform Packaging
Generating Static Boot Image
Platform Packaging
Next Step
Fast Track
Step 3: Test the Platform
Test 1: Read Platform Info
Test 2: Test PL kernels on the DFX platform
Create a Vector-Addition application
Test the Application on Hardware Emulation
Test the Application on Hardware
Test 3: Run an AI Engine + PL Acceleration Application Project
Create an AI Engine and PL System Design
Test the Application on Hardware Emulation
Test the Application on Hardware
Test the reconfiguration feature on hardware
Next Steps
What’s Next
Iteration Guidelines
Frequently Asked Questions
SError Interrupt on xrt_cu_hls_init
ERROR: [BD 41-2666] NoC BDC Aperture Error: Dead-end Aperture
Custom Kria SOM Platform Creation Example
Step 1: Create the Vivado Hardware Design and Generate XSA
Create Base Vivado Project from Preset
Customize System Design for Clock and Reset
Add Interrupt Support
Enable AXI Interfaces for the Platform
Modify the IP address in address editor (Optional)
Export Hardware XSA
Next Step
Step 2: Create the Vitis platform
Prepare the Common Image
Generate Software Components from the KV260 Starter Kit BSP(Optional)
Generate Device Tree Overlay
Create the Vitis Platform
Next Step
Step 3: Test the Platform
Test 1: Read Platform Info
Test 2: Run Vector Addition Application
Congratulations
Fast Track
Next Steps
Iteration Guidelines

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