Project Creation - 2023.2 English

1. Create a workspace and Launch Vivado if you haven’t

   1. mkdir WorkSpace.

   2. cd WorkSpace.

   3. un source <Vitis_Install_Directory>/settings64.sh to set up the Vivado running environment.

   4. Run Vivado by typing vivado in the console.

2. Download the Versal Extensible Embedded Platform Example

   1. Click Tools -> Vivado Store..

   2. Click OK to agree to download open source examples from web.

   3. Select Example Designs -> Platforms -> Versal DFX Extensible Embedded Platform and click the download button on the tool bar.

   4. Click Close after installation complete.

3. Create the Versal DFX Extensible Embedded Platform Example project.

   1. Click File -> Project -> Open Example….

   2. Click Next.

   3. Select Versal DFX Extensible Embedded Platform in the Select Project Template window.

   4. Input project name and project location. Keep Create project subdirectory checked. Click Next.

   5. Select target board in Default Part window. In this example, Versal VCK190 Evaluation Platform is used. Click Next.

      

   6. Configure Clocks Settings. You can enable more clocks, update output frequency and define default clock in this view for the static region. In this example, you can retain the default settings.

   7. Configure Interrupt Settings. You can choose the number of interrupts. 63 interrupts will use two AXI_INTC in cascade mode. In this example, you can retain the default setting.

   8. Configure Memory Settings. By default, the example design will enable the on board DDR4. If you select the additional on board memories option, you will enable the LPDDR4 on board.

   9. Click Next.

   10. Review the new project summary and click Finish.

   11. After a while, you will see the design example has been generated.

The generated design is shown in the following figure:

At this stage, the Vivado block automation has already created a top block design and a dynamic region block. It added the CIPS, AXI NOC block, dfx_decoupler, and supporting logic blocks to the top diagram. It also added the AI engine, AXI NOC and clock in dynamic region (VitisRegion.bd) and also applied all board presets for the VCK190. Block generation and address aperture setting has also been done. In the following sections, we will delve into the sub-modules within this CED DFX platform. The sub-module design methodology is a fundamental aspect applied to all DFX designs.