write_sdf - 2020.2 English

Vivado Design Suite Tcl Command Reference Guide (UG835)
Document ID
UG835
Release Date
2020-11-18
Version
2020.2 English

write_sdf command generates flat sdf delay files for event simulation

Syntax

write_sdf [‑process_corner <arg>] [‑cell <arg>] [‑rename_top <arg>]
    [‑force] [‑mode <arg>] [‑gzip] [‑multithread <arg>] [‑quiet] [‑verbose]
    <file>

Usage

Name Description
[-process_corner] Specify process corner for which SDF delays are required; Values: slow, fast Default: slow
[-cell] Root of the design to write, e.g. des.subblk.cpu Default: whole design
[-rename_top] Replace name of top module with custom name e.g. netlist Default: new top module name
[-force] Overwrite existing SDF file
[-mode] Specify sta (Static Timing Analysis) or timesim (Timing Simulation) mode for SDF Default: timesim
[-gzip] write gzipped SDF
[-multithread] Run in multithread mode with specified number of threads Default: -1
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
<file> File name

Categories

FileIO, Simulation, Timing

Description

Writes the timing delays for cells in the design to a Standard Delay Format (SDF) file.

The output SDF file can be used by the write_verilog command to create Verilog netlists for static timing analysis and timing simulation.

Arguments

-process_corner [ fast | slow ] - (Optional) Write delays for a specified process corner. Delays are greater in the slow process corner than in the fast process corner. Valid values are 'slow' or 'fast'. By default, the SDF file is written for the slow process corner.

-cell <arg> - (Optional) Write the SDF file from a specific cell of the design hierarchy. The default is to create an SDF file for the whole design.

-rename_top <arg> - (Optional) Rename the top module in the output SDF file as specified.

-force - (Optional) Forces the overwrite of an existing SDF file of the same name.

-mode [ timesim | sta ]- (Optional) Specifies the mode to use when writing the SDF file. Valid values are:
  • timesim - Output an SDF file to be used for timing simulation. This is the default setting.
  • sta - Output an SDF file to be used for static timing analysis (STA).
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.
<file> - (Required) The file name of the SDF file to write. The SDF file is referenced in the Verilog netlist by the use of the -sdf_anno and -sdf_file arguments of the write_verilog command.
Note: If the path is not specified as part of the file name, the file will be written into the current working directory, or the directory from which the tool was launched.

Examples

The following example writes an SDF file to the specified directory: 
write_sdf C:/Data/FPGA_Design/designOut.sdf

See Also