Calculate device configuration time (ms)
Syntax
calc_config_time [‑verbose] [‑max] [‑min] [‑typical] [‑por_used]
[‑por_ramp <arg>] [‑clk_freq <arg>] [‑bitstream_size <arg>] [‑quiet]Returns
Report
Usage
| Name | Description |
|---|---|
[-verbose]
|
Print out calculation parameters |
[-max]
|
Calculate Maximum Configuration Time |
[-min]
|
Calculate Minimum Configuration Time |
[-typical]
|
Calculate Typical Configuration Time |
[-por_used]
|
(Deprecated) Specify if Power On Reset (POR) is used by using a non-zero por_ramp |
[-por_ramp]
|
Specify a Power On Reset (POR) ramp rate as 1 ms to 50 ms Default: 0 ms |
[-clk_freq]
|
Specify a clock frequency for Slave mode, or for Master mode if using external master clock (MHz) Default: 0 MHz |
[-bitstream_size]
|
Specify a bitstream size to override the default Default: 0 |
[-quiet]
|
Ignore command errors |
Categories
Description
Some applications require that the Xilinx device be configured and operational within a short time. This command lets you estimate the configuration time for the device and design in question. The configuration time includes the device initialization time plus the configuration time. Configuration time depends on the size of the device and speed of the configuration logic. For more information on the configuration time refer to UltraFast Design Methodology Guide for the Vivado Design Suite (UG949), the UltraScale Architecture Configuration User Guide (UG570), or the 7 Series FPGAs Configuration User Guide (UG470).
Some of the settings needed to calculate the configuration time are stored as properties on the current design, such as the BITSTREAM.CONFIG.CONFIGRATE or BITSTREAM.CONFIG.EXTMASTERCCLK_EN properties. In some master modes, the FPGA provides the configuration clock to control configuration, with the nominal configuration clock frequency specified by BITSTREAM.CONFIG.CONFIGRATE. The property can be defined in the Edit Device Properties dialog box of the Vivado Design Suite IDE, or by using set_property to directly set the value of the specified property.
For a slave configuration mode, or for configuration modes using an external master clock, the needed clock frequency is specified by the -clk_freq option.
This command returns a value in milliseconds if successful, or returns an error if it fails.
Arguments
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
set_msg_config command.
-max - (Optional) Reports the maximum configuration time as estimated by the command.
-min - (Optional) Reports the minimum configuration time as estimated by the command.
-typical - (Optional, default) Reports the typical configuration time as estimated by the command.
-por_ramp <arg> - (Optional) Specify the power-on reset (POR) ramp rate as a value from 1 millisecond (ms) to 50 ms. The default is 0. You can reduce the power on reset time (Tpor) by controlling the ramp rate on the system. For specifications on the Tpor ramp options, see the FPGA configuration switching characteristics in the data sheet of the specific device in use.
-clk_freq <arg> - (Optional) Specify a clock frequency in MHz for Slave mode, or when using an external master clock. The default is 0.
-por_used <arg> - (Deprecated) Specify if a Power On Reset (POR) is used. Replaced by using a non-zero por_ramp command line option.
-bitstream_size <arg> - (Optional) Specify a bitstream size in bits. Default is the design bitstream size.
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Example
calc_config_time -max -clk_freq 50