Open a connection to a hardware target on the hardware server
Syntax
open_hw_target [‑jtag_mode <arg>] [‑xvc_url <arg>] [‑auto_calibrate]
[‑quiet] [‑verbose] [<hw_target>]Usage
| Name | Description |
|---|---|
[-jtag_mode]
|
Open target in JTAG mode |
[-xvc_url]
|
Open target connection to XVC server |
[-auto_calibrate]
|
Auto-calibrate target for optimal frequency (SmartLynq cable only) |
[-quiet]
|
Ignore command errors |
[-verbose]
|
Suspend message limits during command execution |
[<hw_target>]
|
hardware target Default: current hardware target |
Categories
Description
Opens a connection to the specified hardware target of the connected hardware servers, or opens the current hardware target.
The hardware target is a system board containing a JTAG chain of one or more Xilinx devices that you can program with a bitstream file, or use to debug your design. Connections between hardware targets on the system board and the Vivado Design Suite are managed by the Xilinx hardware server application, and the connect_hw_server command. Refer to Vivado Design Suite User Guide: Programming and Debugging (UG908) for a list of supported JTAG download cables and devices.
Each hardware target can have one or more Xilinx devices to program, or to use for debugging purposes. The current device is specified or returned by the current_hw_device command.
Use the open_hw_target command to open a connection to one of the available hardware targets. The open target is automatically defined as the current hardware target. Alternatively, you can define the current target with the current_hw_target command, and then open the current target. The Vivado Design Suite directs programming and debug commands to the open target through the hardware server connection.
An open connection to the hardware target can be closed using the close_hw_target command.
The open_hw_target command returns connection messages from the hardware server, or returns an error if it fails.
Arguments
-jtag_mode [ on | off ] - (Optional) Open the hardware target in JTAG mode for accessing boundary scan. When the target is running in JTAG mode the Instruction Register (IR) and Data Registers (DR) are accessible through the scan_ir_hw_jtag and scan_dr_hw_jtag commands, and the devices on the target can also be put into various states using the run_state_hw_jtag command.
hw_target object that can also be enabled using values of "1" or "True".-xvc_url arg - (Optional) Open the hardware target as a connection to a Xilinx Virtual Cable. Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable, and lets you access and debug your Xilinx device without using a physical cable. The argument takes the IP address and port number of the xvcServer application.
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
set_msg_config command.<hw_target> - (Optional) Specify the hw_target object to open a connection to for programming and debug. The hw_target must be specified as an object as returned by the get_hw_targets or current_hw_target commands. If no target is specified, the Vivado Design Suite will open a connection to the current_hw_target.
Example
get_hw_targets command:
open_hw_target [lindex [get_hw_targets] 0]open_hw
connect_hw_server -url jupiter:3121
current_hw_target [get_hw_targets */xilinx_tcf/Digilent/210203327463A]
open_hw_target -jtag_mode on