read_verilog - 2020.2 English

Read one or more Verilog files

Syntax

read_verilog [‑library <arg>] [‑sv] [‑quiet] [‑verbose] <files>...

Returns

list of file objects that were added

Usage

Name	Description
`[-library]`	Library name (ignored by Vivado synthesis) Default: default lib
`[-sv]`	Enable system verilog compilation
`[-quiet]`	Ignore command errors
`[-verbose]`	Suspend message limits during command execution
`<files>`	Verilog file name(s)

Description

Reads Verilog or SystemVerilog source files. This command is similar to the add_files command. The Verilog file is added to the source fileset as it is read. If the -library argument is specified, the file is added with the Library property defined appropriately.

You can use this command to read the contents of source files into the in-memory design, when running the Vivado tool in Non Project mode, in which there is no project file to maintain and manage the various project source files. Refer to the Vivado Design Suite User Guide: Design Flows Overview (UG892) for more information on Non Project mode.

Because SystemVerilog is a superset of the Verilog language, the read_verilog command can read both file types. However, for SystemVerilog files, the -sv option needs to be specified for read_verilog to enable compilation in the SystemVerilog mode. In this mode, the tool recognizes and honors the SystemVerilog keywords and constructs.

You can have a mixture of both Verilog files (.v files), and SystemVerilog files (.sv files), as well as VHDL (using read_vhdl). When the tool compiles these files for synthesis, it creates separate "compilation units" for each file type. All files of the same type are compiled together.

Arguments

-library <arg> - (Optional) The library the Verilog file should reference. The default Verilog library is xil_defaultlib. The library name is ignored by Vivado synthesis.

-sv -(Optional) Read the files as a SystemVerilog compilation group.

Note: Since Verilog is a subset of SystemVerilog, unless a Verilog source has user-defined names that collide with reserved SystemVerilog keywords, reading Verilog files with the -sv switch enables SystemVerilog compilation mode for those files. However, adding a SystemVerilog file in a Verilog compilation unit (without -sv) will not work.

<files> - (Required) The name of one or more Verilog files to be read.

Note: If the path is not specified as part of the file name, the tool will search for the specified file in the current working directory and then in the directory from which the tool was launched.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.

Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.

-verbose - (Optional) Temporarily override any message limits and return all messages from this command.

Note: Message limits can be defined with the set_msg_config command.

Examples

The following example reads the specified Verilog file and adds it to the source fileset:

read_verilog C:/Data/FPGA_Design/new_module.v

The following example creates two compilation units, one for SystemVerilog files and one for Verilog files:

read_verilog -sv { file1.sv file2.sv file3.sv }  
read_verilog { file1.v file2.v file3.v}