compile_simlib - 2020.2 English

Vivado Design Suite Tcl Command Reference Guide (UG835)
Document ID
UG835
Release Date
2020-11-18
Version
2020.2 English

Compile simulation libraries

Syntax

compile_simlib [‑directory <arg>] [‑family <arg>] [‑force]
    [‑language <arg>] [‑library <arg>] [‑print_library_info <arg>]
    ‑simulator <arg> [‑simulator_exec_path <arg>] [‑gcc_exec_path <arg>]
    [‑source_library_path <arg>] [‑no_ip_compile] [‑32bit]
    [‑no_systemc_compile] [‑no_dpi_compile] [‑quiet] [‑verbose]

Usage

Name Description
[-directory] Directory path for saving the compiled results Default: .
[-family] Select device architecture Default: all
[-force] Overwrite the pre-compiled libraries
[-language] Compile libraries for this language Default: all
[-library] Select library to compile Default: all
[-print_library_info] Print Pre-Compiled library information
-simulator Compile libraries for this simulator
[-simulator_exec_path] Use simulator executables from this directory
[-gcc_exec_path] Use GNU executables from this directory
[-source_library_path] If specified, this directory will be searched for the library source files before searching the default path(s) found in environment variable XILINX_VIVADO for Vivado
[-no_ip_compile] Do not compile IP static files from repository
[-32bit] Perform the 32-bit compilation
[-no_systemc_compile] Do not compile models for system simulation
[-no_dpi_compile] Do not compile DPI models
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution

Categories

Simulation

Description

Compile Xilinx® simulation libraries for the cells and IP used in the current project, or from a specified directory for use in multiple design projects.

The Vivado Design Suite provides simulation models as a set of files and libraries that contain the behavioral and timing models for use by the Vivado simulator. The compile_simlib command compiles these libraries for use by third-party simulators prior to design simulation. Libraries must generally be compiled or recompiled with a new software release to update simulation models and to support a new version of a simulator.

Important: You should rerun the compile_simlib command any time a new third party simulator will be used, or a new Vivado Design Suite version or update is installed.

When this command is run from a current project, the tool will use the device family, target language, and library settings specified by the project as the default values, rather than the default settings of the command defined below. The default settings can be overridden by specifying the necessary options when the command is run.

The compile_simlib command uses simulator compilation directives when compiling the simulation libraries. You can edit the default configuration settings using the config_compile_simlib command.

The command returns information related to the compiled libraries, or an error if it fails.

Arguments

-directory <arg> - (Optional) Directory path for saving the compiled library results.
Note: By default, the libraries are saved in the current working directory in Non-Project mode, and the libraries are saved in <project>/<project>.cache/compile_simlib directory in Project mode. Refer to the Vivado Design Suite User Guide: Design Flows Overview (UG892) for more information on Project and Non-Project modes.

-family <arg> - (Optional) Compile simulation libraries for the specified device family. If this switch is not specified, the libraries for all families will be compiled.

<arg>: all, kintex7, virtex7, artix7, spartan7, zynq, kintexu, kintexuplus, virtexu, virtexuplus, zynquplus, zynquplusrfsoc, versal
  • all (generate libraries for all device families, the default)
  • kintex7 - Kintex-7 family
  • virtex7 - Virtex-7 family
  • artix7 - Artix®-7 family
  • spartan7 - Spartan-7 family
  • zynq - Zynq-7000 family
  • kintexu - Kintex UltraScale family
  • kintexuplus - Kintex® UltraScale+ family
  • virtexu - Virtex UltraScale™ family
  • virtexuplus - Virtex® UltraScale+™ family
  • zynquplus - Zynq® UltraScale+ family
  • zynquplusrfsoc - Zynq® UltraScale+ RFSoCs family
  • versal - Versal™ ACAP family

-force - (Optional) Overwrite the current pre-compiled libraries.

-language [ verilog | vhdl | all ] - (Optional) This option is only needed for use with -no_ip_compile, and will compile base simulation libraries for the specified language. If this option is not specified then the language will be set according to the simulator selected with -simulator. For multi-language simulators both Verilog and VHDL libraries will be compiled.
Tip: By default, compile_simlib compiles simulation libraries for IP, and compiles all languages for the IP.
-library <arg> - (Optional) Specify the simulation library to compile. As a default, the compile_simlib command will compile all simulation libraries. Valid values are:
  • all (the default)
  • unisim
  • simprim
To specify multiple libraries, repeat the -lib options for each library. For example: 
.. -library unisim -library simprim ..

-print_library_info - (Optional) Print the library information for the compiled simulation library.

-simulator <arg> - (Required) Compile simulation libraries for the specified simulator.

<arg>: modelsim, questa (or questasim), ies, xcelium, vcs (or vcs_mx), riviera, activehdl (or active_hdl)
  • modelsim - ModelSim Simulator version 2020.2 or later
  • questa - Questa Advanced Simulator version 2020.2 or later
  • ies - (Linux only) Incisive Enterprise Simulator version 15.20.083 or later
  • xcelium - (Linux only) Xcelium Parallel Simulator version 20.03.005 or later
  • vcs_mx - (Linux only) Verilog Compiler Simulator version Q-2020.03 or later
  • riviera - Riviera-PRO Simulator version 2020.04 or later
  • activehdl - (Windows only) Active-HDL Simulator version 11.1

-simulator_exec_path <arg> - (Optional) Specify the directory to locate the third-party compiler and simulator executables. This option is required if the target simulator is not specified in the $PATH or %PATH% environment variable; or to override the path from the $PATH or %PATH% environment variable.

-gcc_exec_path <arg> - (Optional) Specify the directory to locate the third-party simulator GCC executables. If this switch is not specified, then the directory path will be determined from the path set by the GCC_SIM_EXE_PATH environment variable. If this variable is not set, then compile_simlib will automatically try to calculate the path from the simulator installation. If not able to determine, the path will be then searched from the $PATH (Linux) or %PATH% (Windows) environment variable.

Supported GCC versions.
  • questa - 5.3.0
  • xcelium - 6.3
  • vcs - 6.2.0
-source_library_path <arg> - (Optional) If specified, this directory will be searched for the library source files before searching the default path(s) defined by the environment variables ($XILINX or $XILINX_VIVADO).
Note: Do not use this option unless explicitly instructed to by Xilinx Technical Support.

-no_ip_compile - (Optional) Disables the compilation of simulation files for IP in the design or the specified repositories. By default, the compile_simlib command compiles the static simulation files for all IP in the IP catalog, including added user and third-party repositories. Use this option to disable that feature.

-32bit - (Optional) Perform simulator compilation in 32-bit mode instead of the default 64-bit compilation.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

Examples

The following example shows how to compile UNISIM and SIMPRIM libraries for ModelSim (VHDL) for a design using a Virtex-7 device: 
compile_simlib -simulator modelsim -family virtex7 -library unisim \  
   -library simprim -language vhdl

See Also