report_stacks - 2020.2 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2020-11-18
Version
2020.2 English

Print names of processes in a design, which are waiting inside a subprogram, in textual format

Syntax

report_stacks [‑of_instance <arg>] [‑quiet] [‑verbose]

Returns

Returns string

Usage

Name Description
[-of_instance] Default: NULL
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution

Categories

Simulation

Description

Print name of the HDL process scopes waiting inside a subprogram in textual format.

Arguments

-of_instance - (Optional) Specifies the instance to report the stacks from.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

Examples

Example design:
module top; 
 
       int i; 
 
       function void f(input int in1); 
           automatic int a; 
           a = in1 + 7; 
           $display($time, " in f :: a %d in1 %d ", a, in1); 
       endfunction 
 
       task automatic t(input int in2); 
           int b; 
           b = in2 + 10; 
           $display($time, " in t :: in2 %d b %d ", in2, b); 
           #5; 
           f(b);    // Case C 
           $display($time, " Back in t : after wait and f(%d) ", b); 
       endtask 
 
       initial begin                         // "/top/Initial18_0" 
           $display($time, " in initial 1 "); 
           i = 200; 
           t(i);        // Case B 
           $display($time, " Back in initial 1 after t(%d) ", i); 
       end 
 
       initial begin                         // "/top/Initial25_1" 
           $display($time, " in initial 2 "); 
           #2; 
           f(50);       // Case A 
           $display($time, " Back in initial 2 after f(50) "); 
       end 
   endmodule 

When simulation is stopped inside function "f" for its call at 'Case A' , the two processes /top/Initial18_0 and /top/Initial25_1, are waiting inside task "t" (call at 'CaseB') and function "f" (call at 'CaseA') respectively.

1. > report_stacks 
   Verilog Process: {/top/Initial18_0} 
   Verilog Process: {/top/Initial25_1}   

See Also