Set output delay on ports
Syntax
set_output_delay [‑clock <args>] [‑reference_pin <args>] [‑clock_fall]
[‑rise] [‑fall] [‑max] [‑min] [‑add_delay] [‑network_latency_included]
[‑source_latency_included] [‑quiet] [‑verbose] <delay> <objects>Usage
| Name | Description |
|---|---|
[-clock]
|
Relative clock |
[-reference_pin]
|
Relative pin or port |
[-clock_fall]
|
Delay is relative to falling edge of clock |
[-rise]
|
Specifies rising delay |
[-fall]
|
Specifies falling delay |
[-max]
|
Specifies maximum delay |
[-min]
|
Specifies minimum delay |
[-add_delay]
|
Don't remove existing input delay |
[-network_latency_included]
|
Specifies network latency of clock already included |
[-source_latency_included]
|
Specifies source latency of clock already included |
[-quiet]
|
Ignore command errors |
[-verbose]
|
Suspend message limits during command execution |
<delay>
|
Delay value |
<objects>
|
List of ports |
Description
Specifies the external system-level path delay on a primary output port relative to a clock edge at the interface of the design. The output delay value is specified in nanoseconds (ns), and can be positive or negative, depending on the clock and data relative phase outside the FPGA device.
To accurately model the system-level timing of your Xilinx FPGA design, you must assign timing delays for objects external to the FPGA onto the primary input or output ports in your design. These delays are defined by the set_input_delay and set_output_delay commands.
set_max_delay constraint assigned, the specified output delay value is considered part of the max_delay computation. That is, the output delay consumes a portion of the max delay on the timing path that includes the output port.This command returns nothing if successful, or returns an error if it fails.
Arguments
-clock <arg> - (Optional) Indicates that the delay is relative to the rising edge of the specified clock.
-reference_pin <arg> - (Optional) Specifies that the delay is relative to the specified pin rather than a clock.
-clock_fall - (Optional) Specifies that the delay is relative to a falling edge of the clock rather than rising edge.
-rise - (Optional) Specifies that the delay is for a rising edge.
-fall - (Optional) Specifies that the delay is for a falling edge
-max - (Optional) Specifies that the delay specified should be treated as a maximum threshold.
-min - (Optional) Specifies that the delay specified should be treated as a minimum threshold.
-add_delay - (Optional) Add the specified delay constraint to the port, to coexist with any other set_output_delay constraints already defined on the port. The default behavior is to replace the existing delays.
-network_latency_included - (Optional) Indicates that the clock network latency of the reference clock is included in the delay value. The Vivado timing engine considers the clock edge reaching the capture flop after the clock latencies unless the specified input or output delay value includes the source latency or network latency.
-source_latency_included - (Optional) Specifies that the source latency of the reference clock is included in the specified delay value.
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
set_msg_config command.<delay> - (Optional) The delay specified in nanoseconds (ns) to apply to the listed ports. Valid values are floating point numbers, with a default value of 0.
<objects> - (Required) A list of ports to which the delay applies.
Examples
set_output_delay 5.0 -clock [get_clocks cpuClk] [get_ports] set_output_delay 5.0 -clock [get_clocks cpuClk] \
-network_latency_included [get_ports] create_clock -name clk_ddr -period 6 [get_ports DDR_CLK_IN]
set_output_delay -clock clk_ddr -max 2.1 [get_ports DDR_OUT]
set_output_delay -clock clk_ddr -max 1.9 [get_ports DDR_OUT] -clock_fall -add_delay
set_output_delay -clock clk_ddr -min 0.9 [get_ports DDR_OUT]
set_output_delay -clock clk_ddr -min 1.1 [get_ports DDR_OUT] -clock_fall -add_delay-add_delay option allows the new min and max delay constraints to exist alongside the first delays on the same port.