set_false_path - 2024.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2024-05-30
Version
2024.1 English

Define false path

Syntax

set_false_path [‑setup] [‑hold] [‑rise] [‑fall] [‑reset_path]
    [‑from <args>] [‑rise_from <args>] [‑fall_from <args>] [‑to <args>]
    [‑rise_to <args>] [‑fall_to <args>] [‑through <args>]
    [‑rise_through <args>] [‑fall_through <args>] [‑quiet] [‑verbose]

Usage

Name Description
[-setup] Eliminate setup timing analysis for paths
[-hold] Eliminate hold timing analysis for paths
[-rise] Eliminate only rising delays for the defined paths
[-fall] Eliminate only falling delays for the defined paths
[-reset_path] Reset this path before setting false path
[-from] List of path startpoints or clocks
[-rise_from] Apply to paths rising from the list of startpoints or clocks
[-fall_from] Apply to paths falling from the list of startpoints or clocks
[-to] List of path endpoints or clocks
[-rise_to] Apply to paths with rise transition at the list of endpoints or clocks
[-fall_to] Apply to paths with fall transition at the list of endpoints or clocks
[-through] List of through pins, cells or nets
[-rise_through] Apply to paths rising through pins, cells or nets
[-fall_through] Apply to paths falling through pins, cells or nets
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution

Categories

SDC, XDC

Description

Tip: The XDC > Timing Constraints language templates and the Timing Constraints Wizard in the Vivado™ IDE offer timing diagrams and additional details around defining specific timing constraints. You can refer to these sources for additional information.

Sets false timing paths in the design that are ignored during timing analysis.

Note: This command operates silently and does not return direct feedback of its operation

Arguments

-setup - (Optional) Eliminate setup timing analysis for specified timing paths.

-hold - (Optional) Eliminate hold timing analysis for specified timing paths.

-rise - (Optional) Eliminate rising delays for the specified timing paths.

-fall - (Optional) Eliminate falling delays for the specified timing paths.

-reset_path - (Optional) Reset the timing path before setting false path. This clears all exception-based timing constraints from the defined timing path.

-from <element_name> - (Optional) List of path origins or clocks. A valid startpoint is a clock object, the clock pin of sequential logic, or an input or bidirectional port.

-rise_from <element_name> - (Optional) Apply to paths rising from the list of origins or clocks

-fall_from <element_name> - (Optional) Apply to paths falling from the list of origins or clocks

-to <element_name> - (Optional) List of path endpoints or clocks

-rise_to <element_name> - (Optional) Apply to paths with rise transition at the list of endpoints or clocks

-fall_to <element_name> - (Optional) Apply to paths with fall transition at the list of endpoints or clocks

-through <element_name> - (Optional) List of through pins, cells or nets

-rise_through <element_name> - (Optional) Apply to paths rising through pins, cells or nets

-fall_through <element_name> - (Optional) Apply to paths falling through pins, cells or nets

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

Examples

The following example eliminates the setup timing for paths from the bftClk:

set_false_path -setup -from bftClk

The following example excludes paths between the two clocks from timing analysis:

set_false_path -from [get_clocks GT0_RXUSRCLK2_OUT] \
   -to [get_clocks DRPCLK_OUT]