create_debug_core - 2024.2 English

Description

Adds a new Integrated Logic Analyzer (ILA) debug core to an open netlist design in the current project. The ILA debug core defines ports for connecting nets to for debugging the design in the logic analyzer feature of the Vivado™ Design Suite available through the open_hw command.

ILA debug cores can be added to the RTL source files of the design using debug cores from the Xilinx™ IP catalog, or added to the netlist design after synthesis using this command. Refer to the Vivado Design Suite User Guide: Vivado Programming and Debugging (UG908) for more information on using ILA debug cores.

The ILA core is created with a CLK port and a PROBE port by default. The CLK port defines the clock domain for the ILA core, and allows you to probe signals that are common to that domain. The CLK port only supports one clock signal, and so you must create a separate debug core for each clock domain. The PROBE port provides a probe point for nets marked for debug with the MARK_DEBUG property. The PROBE port offers multiple channels to probe multiple nets from a single ILA core.

You can add new ports to an existing ILA core with the create_debug_port command, and connect signals to the ports using the connect_debug_port command.

Arguments

<name> - (Required) The name of the ILA debug core to add to the project.

<type> - (Required) The type of debug core to insert. Only the ILA debug core is currently supported in the Vivado™ tool. The ILA debug core simply adds another load onto a connected net without otherwise altering it.

Examples

The following example opens the synthesis run, creating the specified netlist design name, and then creates a new ILA debug core in that design:

open_run -name netlist_1 synth_1
create_debug_core myCore ila

The properties of the debug core can be customized by using the set_property command as in the following example:

set_property C_DATA_DEPTH 2048 [get_debug_cores myCore]

This example marks a sequence of nets for debugging using the MARK_DEBUG property, creates a new debug core, connects the CLK port to the appropriate clock domain, and assigns the debug nets to the PROBE ports on the core:

set_property MARK_DEBUG true [get_nets [list {control_reg[0]} {control_reg[1]} \
   {control_reg[2]} {control_reg[3]} {control_reg[4]} {control_reg[5]} \
   {control_reg[6]} {control_reg[7]} {control_reg[8]} {control_reg[9]} \
   {control_reg[10]} {control_reg[11]} {control_reg[12]} {control_reg[13]} \
   {control_reg[14]} {control_reg[15]} {control_reg[16]} {control_reg[17]} \
   {control_reg[18]} {control_reg[19]} {control_reg[20]} {control_reg[21]} \
   {control_reg[22]} {control_reg[23]} {control_reg[24]} {control_reg[25]} \
   {control_reg[26]} {control_reg[27]} {control_reg[28]} {control_reg[29]} \
   {control_reg[30]} {control_reg[31]}]]
create_debug_core u_ila_0 ila
set_property port_width 1 [get_debug_ports u_ila_0/CLK]
connect_debug_port u_ila_0/CLK [get_nets [list wbClk ]]
set_property port_width 32 [get_debug_ports u_ila_0/PROBE0]
connect_debug_port u_ila_0/PROBE0 [get_nets [list {control_reg[0]}
   {control_reg[1]} {control_reg[2]} {control_reg[3]} {control_reg[4]} \
   {control_reg[5]} {control_reg[6]} {control_reg[7]} {control_reg[8]} \
   {control_reg[9]} {control_reg[10]} {control_reg[11]} {control_reg[12]} \
   {control_reg[13]} {control_reg[14]} {control_reg[15]} {control_reg[16]} \
   {control_reg[17]} {control_reg[18]} {control_reg[19]} {control_reg[20]} \
   {control_reg[21]} {control_reg[22]} {control_reg[23]} {control_reg[24]} \
   {control_reg[25]} {control_reg[26]} {control_reg[27]} {control_reg[28]} \
   {control_reg[29]} {control_reg[30]} {control_reg[31]} ]]

See Also

• connect_debug_port
• create_debug_port
• delete_debug_core
• get_debug_cores
• implement_debug_core
• open_run
• report_debug_core
• report_property
• set_property