Call IP Services to regenerate an IP, then stitch it into the current netlist
Syntax
implement_xphy_cores [‑output_dir <arg>] [‑rtl_only] [‑force]
[‑debug_output] [‑update_delay_value_only] [‑quiet] [‑verbose]Usage
| Name | Description |
|---|---|
[-output_dir]
|
Target Output Directory for PHY IP Generated Files Default: empty |
[-rtl_only]
|
Run the complete process to generate the PHY RTL code but do not replace the PHY core netlist |
[-force]
|
Implement all non-optimized memory cores. When use with -rtl_only, optimized cores will be included, as well. |
[-debug_output]
|
Enable debugging output. |
[-update_delay_value_only]
|
Update latest Delay value. |
[-quiet]
|
Ignore command errors |
[-verbose]
|
Suspend message limits during command execution |
Categories
Implements the memory IP cores and Advanced IO Wizard cores in the current project which use XPHY Logic. Memory IP included in the AMD Vivado Design Suite IP catalog generates memory controllers and interfaces for AMD devices. Memory IP includes different IP cores from the Vivado IP catalog depending on the device architecture and specified memory interface.
The implement_xphy_cores command generates the RTL information for
the physical interface (PHY) of the memory controller or Advanced IO Wizard
interface and integrates the synthesized netlist of the memory controller into the
top-level design.
launch_runs command or
running opt_design automatically implements Memory IPs and Advanced
IO Wizard interfaces. The implement_xphy_cores command integrates
the memory IP or Advanced IO Wizard interface without implementing the entire
design.implement_xphy_cores command, otherwise it returns an
error. You can use report_drc to check the status of the memory
controller.For soft memory controllers, refer to the Versal ACAP Soft RLDRAM 3 Memory Controller (PG354), Versal ACAP Soft QDR-IV SRAM Memory Controller (PG355), and Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller (PG353) LogiCORE IP Product Guides. For hardened memory controllers, refer to the Versal Adaptive SoC Programmable NoC and Integrated Memory Controller LogiCORE IP Product Guide (PG313). For more information on the Advanced IO Wizard IP, see the Advanced IO Wizard Product Guide (PG320).
Arguments
-output_dir <arg> - (Optional) Specifies the output directory for
the generated output products of the memory IP. If -output_dir is
not specified, the output is generated to the current project folders.
-rtl_only - (Optional) Generates only the PHY RTL information for
the memory controller.
-force - (Optional) Forces the implementation of the memory IP even
if it is latest.
-debug_output - (Optional) Enables the debugging feature of the
memory IP.
-update_delay_value_only - (Optional) Updates latest delay value of
either input or output data pins of PHY IP in picoseconds.
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
set_msg_config command.Examples
The following example implements the memory IP cores in the current design:
implement_xphy_cores