implement_xphy_cores - 2024.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

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2024.1 English

Call IP Services to regenerate an IP, then stitch it into the current netlist


implement_xphy_cores [‑output_dir <arg>] [‑rtl_only] [‑force]
    [‑debug_output] [‑update_delay_value_only] [‑quiet] [‑verbose]


Name Description
[-output_dir] Target Output Directory for PHY IP Generated Files Default: empty
[-rtl_only] Run the complete process to generate the PHY RTL code but do not replace the PHY core netlist
[-force] Implement all non-optimized memory cores. When use with -rtl_only, optimized cores will be included, as well.
[-debug_output] Enable debugging output.
[-update_delay_value_only] Update latest Delay value.
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution



Implements the memory IP cores and Advanced IO Wizard cores in the current project that utilize XPHY Logic.

Memory IP included in the Xilinx™ IP catalog are used to generate memory controllers and interfaces for Xilinx devices. Memory IP includes different IP cores from the Xilinx IP catalog depending on the memory interface specified. More details can be found in the product guides for the individual Memory IP. For soft memory controllers, refer to the Versal ACAP RLDRAM 3 (PG354), QDR-IV (PG355), and DDR4 (PG353) product guides.

Tip: For hardened memory controllers, refer to the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).

Advanced IO Wizard IP is included in the Xilinx IP catalog and are used to generate non-memory high-speed IO interfaces for Xilinx devices. For more information on the Advanced IO Wizard IP see the Advanced IO Wizard Product Guide (PG320).

The implement_xphy_cores command generates the RTL information for the physical interface (PHY) of the memory controller or Advanced IO Wizard interface, and integrates the synthesized netlist of the memory controller into the top-level design. Implementation of the memory IPs and Advanced IO Wizard interfaces is automatic when you launch an implementation run using the launch_runs command, or when you run opt_design. However, you can also use the implement_xphy_cores command to integrate the memory IP or Advanced IO Wizard interface without having to implement the whole design.

Note: All pins of the memory controller and Advanced IO Wizard interface must be assigned prior to running the implement_xphy_cores command, or an error will be returned. You can use report_drc to check the status of the memory controller. This command returns a transcript of its process, or returns an error if it fails.


-update_delay_value_only – (Optional) Deposits the DELAY_VALUE_XPHY attribute value assigned to a port in your design to the proper DELAY_VALUE_x attribute on an XPHY instance for your Advanced IO Wizard interface. The DELAY_VALUE_x attribute on the XPHY interface represents the calibrated input delay or calibrated output delay value in picoseconds corresponding to a particular XPHY input pin DATAIN[x] or XPHY output pin O0[x].

Valid values for the DELAY_VALUE_XPHY port attribute and DELAY_VALUE_x XPHY attribute range from 0 to 625 when the output delay is not used as a cascade. When an input pin uses a cascaded output delay, the valid values for the DELAY_VALUE_XPHY port attribute and DELAY_VALUE_x XPHY attribute range from 0 to 1250. This argument would typically be used in situations when you are tuning an interface in a lab environment on a fully implemented design.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.


The following example opens a fully implemented design checkpoint and then generates two separate device images with calibrated input delay values of 500 and 525 picoseconds to tune the interface. The DELAY_VALUE_XPHY is applied to the port object Datain0_p and then deposited onto the XPHY instance associated with the port using the -update_delay_value_only argument prior to generating the device images.

open_checkpoint advanced_io_wizard_example_routed.dcp

set_property DELAY_VALUE_XPHY 500 [get_ports Datain0_p]
implement_xphy_cores -update_delay_value_only
write_device_image Datain0_500ps.pdi

set_property DELAY_VALUE_XPHY 525 [get_ports Datain0_p]
write_device_image Datain0_525ps.pdi